Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.
9.6.3
Noise Reduction and Noise Estimator
The noise reduction function is a sophisticated successor of the
noise reduction module from the PICNIC-chip, also known as
“LIMERIC”.
Besides the noise reduction part, the Columbus noise
reduction module also comprises a noise estimator. This noise
estimator (the LORE-noise estimator) is a new design with the
ambition of more accuracy and with less control complexity
than the existing noise estimators.
9.7
Video: Scaler Part (Diagram B7, B8 and B9)
The Genesis gm1501 Scaler is a dual channel graphics and
video processing IC for LCD monitors and televisions
incorporating Picture in Picture, up to SXGA output resolutions.
The Scaler controls the display processing in an LCD TV, e.g.
like the deflection circuit in a CRT-based TV. It controls all the
view modes (e.g. like "zooming" and "shifting"). Features like
PC (VGA) or HD inputs, are also handled by this part.
Figure 9-5 Block diagram scaler part
B14
DIGIT
AL IO
B13
MUX-SYNC INTERF
A
CE
B7
SCALER
B11
FLASH/CONTR
OL
B10
SDRAM
B18
ADC
B19
COLUMB
US
(Dig.
P
AL/NTC Comb)
B20
EPLD
B21
EPLD
R_SDTV
G_SDTV
B_SDTV
7E01
SC1_R_CVI_Pr_IN
SC1_G_CVI_Y_IN
SC1_B_CVI_Pb_IN
27
3
7
25
1
5
R_PR+
G_Y+
B_PB+
17
14
11
V_PC
2
H_PC
12
7E03
1
13
Vsync_SDTV
Hsync_SDTV
A
VSYNC
AHSYNC
15
14
7604
5
1
8
4
L4
L3
1F00
15
16
18
23
24
17
+5VSWI
6
14
9
10
11
7
2
1
ANALOG
INPUT
POR
T
D
VI/HDMI
INPUT
POR
T
7B010
K4D263238F
SDRAM
1Mx32x4
F
S
D
ATA
FSADDR
7401
GM1501
GRAPHIC
ZOOM
DISPLA
Y
TIMING
GEN.
VIDEO
ZOOM
OSD CONTROLLER
OUT BLENDER
BRIGHTNESS/CONTRAST/HUE/SA T
EXTERNAL
RO
M
INTERF
A
CE
7C00
MX29L
V040QC
FLASH
RO
M
512Kx8
OCMD
A
T
A
OCMADDR
1P06
1
11
10
12
14
13
15
19
18
20
27
26
28
22
21
23
LVDS_VCC
TXB0-
TXB3+
TXB0+
TXB1-
TXB1+
TXBC+
TXBC-
TXB2-
TXB2+
TXB3-
H_PC
V_PC
BINA|Pb
GINA|YINA
RINA|Pr
HO
TPLUG
RX0-IN
RX0+IN
RXC+IN
RXC-IN
SCL_D
VI
SD
A_D
VI
RX1-IN
RX1+IN
RX2+IN
RX2-IN
FRAME
ST
ORE
CONTR
OL
MICR
O
CONTR
OLLER
UA
R
T
INTERF
A
CE
INTERNAL
RAM
7E02
14
2
11
15
1
12
F624
F625
F626
AE16
AF11
AF16
AF12
AE15
AF15
AE12
AF13
AE14
AF14
B10
A10
N4
N3
B9
A9
B8
A8
AL
B6
AE10
D2
C2
B2
Vsync_SDTV
Hsync_SDTV
INTF_Y_OUT
INTF_U_OUT
INTF_V_OUT
19
PC_HD_DET
D
VI-D
CONNECT
OR
1
8
9
16
17
24
C5
C1
C2
C3
C4
28
8
27
26
25
EF
7L01
EF
7L03
EF
7L02
7L04
MST9883C
A/D
CONV
.
COL_Di(1-7)
COL_Y
A(1-7)
COL_A
COL_D
7M00
T6TU5XBG
COLUMB
US
DIGIT
AL COMB
FIL
TER
DRAM
512Kx16x2
7M01
MSM56V16
+2V5_DDR
95
F_15270_068.eps
200505
48
43
54
30
31
56
57
SCL
SD
A
COL_Do(1-7)
COL_YB(1-7)
7E00
1
13
3
5
2
12
15
14
4
SD_HD_SEL
10,11
C3
SOG
BINA|Pb
GINA|YINA
RINA|Pr
SC1_CV1_DMMI_R_Pr_IN
SC1_CV1_DMMI_G_Y_IN
SC1_CV1_DMMI_B_Pb_IN
B13
B15
B15
B15
B13
B13
B13
B13
SC1_R_CVI_Pr_IN
SC1_G_CVI_Y_IN
SC1_B_CVI_Pb_IN
B2,B13
B2,B13
B2,B13
B13
B13
B13
B3
B3
B3
B14
B14
B14
B3
B13
B14
B14
B13
B3
B9
SCALER
LV
D
S
INTERF
A
CE
RECEIVER
7N04
THC63L
VDF84B
TXB0-
TXB3+
TXB0+
TXB1-
TXB1+
TXBC+
TXBC-
TXB2-
TXB2+
TXB3-
LV
D
S
TRANS-
MITTER
7P02
THC63L
VDM83R
EPLD
PIXEL+
PR
OCESSOR
RGB
7N02
EP1C12F256C8N
OR
RGB
4N03
4N13
4N01
4N15
4N07
4N05
4N17
4N19
4N11
4N09
LVDSAp
LVDSAn
LVDSBp
LVDSBn
LVDSCp
LVDSCn
LVDSDp
LVDSDn
LVDSCLKp
LVDSCLKn
LVDSAp
LVDSAn
LVDSBp
LVDSCp
LVDSCn
LVDSDp
LVDSDn
LVDSCLKp
LVDSCLKn
LVDSBn
OR
LVDSA+
LVDSA-
LVDSB+
LVDSB-
LVDSC+
LVDSC-
LVDSD+
LVDSD-
LVDSCLK-
1P07
1
11
12
13
14
15
16
17
18
19
20
24
25
26
21
22
LVDS_VCC
LVDSA+
LVDSA-
LVDSB+
LVDSB-
LVDSC+
LVDSC-
LVDSD+
LVDSD-
LVDSCLK-
TO PLASMA P
ANEL
TO LCD P
ANEL
Only f
or sets with
PIXEL PLUS
9
9
RGB|CVI_HD
A_SEL
HD
PC
Side-A
V
EXT2
EXT1
TV
PC_HD_DET H H H H L H
SD_HD_SEL H H H H H H
RGB|CVI_HD
A_SEL L H L L L L
SCALER
B7
B7
PC_HD_SEL
I_PC_HD_SEL
R-PR-ADC
G-Y
-ADC
B-PB-ADC
B2
B2
B2
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