7.
Circuit Diagrams and PWB Layouts
SSB: Sync Interface
SYNC INTERFACE
FOR ITV ONLY
(NC)
&
TO SIDE CONNECTORS
RES
RES
RES
RES
RES
RES
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A
B
C
D
E
A
B
C
D
E
1440 D9
1441 E9
2447 E8
2448 E9
2449 E4
3431 A3
3432 B3
3451 A5
3453 B6
3454 B7
3455 C6
3456 C7
3458 D2
3459 D4
3461 E2
3462 E4
3463 C4
4436 A6
4437 B6
4438 D2
4439 E2
4440 D2
4441 E2
5431 E8
6430 A3
6431 B3
7430 B3
7436-1 A6
7436-2 C7
7436-3 D3
7436-4 D4
7436-5 E4
7436-6 E3
I430 B3
I440 C6
I443 B5
I449 D8
I450 D8
I451 E9
I452 E9
I453 B3
I454 B2
0V
3V1
I440
I453
I454
3463
2449
100n
+3V3SW
+3V3SW
100R
3462
100R
4439
3461
4441
100R
3459
+3V3SW
4438
+3V3SW
100R
3458
4440
3456
100R
100R
3454
100R
3455
13
7
14
12
3453
100R
14
10
7436-6
74LVC14APW74LVC14APW
11
7
9
7
14
8
7436-5
74LVC14APW
5
7
14
6
7436-4
74LVC14APW
7
14
4
7436-3
7436-2
74LVC14APW
3
7436-1
74LVC14APW
1
7
14
2
+3V3SW
+3V3SW
4437
4436
I451
I452
I450
I443
I449
6431
1N4148
10p
2448
2447
10p
5431
1
2
3
4
5
+12VSW
1441
S3B-PH-SM4-TB
3432
4K7
3451
+3V3STBY
1440
BM05B-SRSS-TBT
1
2
3
4
5
6
7
I430
BZX384-C2V7
6430
+3V3STBY
+5VSW
7430
PDTC114ET
1K0
3431
COL_HREF
H_DELAY
H_1FH
COL_VA
Vsync_SDTV
V_1FH
SC1_CVBS_RF_OUT
Vsync_SDTV
ITV_IR_SW_RESET
VSYNC
HOUT
Hsync_SDTV
LED_SEL
B3
B3
3139 123 6093.1
F_15270_013.eps
170505
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