Panasonic KX-NS500AG, Руководство по обслуживанию

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KX-NS500AG
4.3. Expansion Unit
The expansion unit is constructed by CPU Board (SPR) and Mother Board. The block diagram and operation of each card are
described here.
4.3.1. CPU Board (SPR)
Fig.4 shows detail block diagram of CPU Board (SPR), and each function of CPU Board (SPR) is described in Table.6.
Table.6 CPU Board (SPR) Function Description
Card Description
CPU CPU controls the line card in the expansion unit by the control from an CPU Board (MPR).
DDR3 DDR3 is main memory of CPU Board (SPR). Operating system, application program and concerning data are
stored in this memory.
NAND Flash CPU program is stored in this memory.
FPGA FPGA provides control and monitoring function of each line card.
A RM
Cortex- A 8
300MH z
L1 3 2 K/3 2 K w / S ED
L 2 2 5 6 K w /ECC
1 76 K ROM 6 4K R A M 6 4K R A M
Crypto
DDR
Inter fa ce
DDR3
1 2 8MB
N A ND
N A ND
FL AS H
2 5 6 MB
U A RT
S D
GPIO
Interrupt
etc.
DC/DC(+3.3 V ,+1.8 V ,+1.1 V )
A C_ A LM, DC_ A LM, S yste m Reset, FPG A _REBOOT, DONE
S l a ve
FPG A
LED
+5 V
Extern a l bus
80
P
IN
C
O
N
NE
C
T
O
R
(C
PU
In
te
r
fa
ce)
S
T
A
TU
S
DC/DC
+3.3 V
+15 V
8bit
8bit
+5 V
+ V B A T
L V D S
Do w n
Hi g h wa y
Up
Hi
g h wa y
FH+CLK
(8MH z )
Interrupt
Exp I/F
R J 45
NETREF
Exp
a
nsi
on
bu
s
Fi g .4 CPU Bo a rd ( S PR) Bloc k Di ag r am