TERMINAL DESCRIPTION(1/10)
PIN LAYOUT
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -43
Q8200: FLI30336 (Video Processor, TORINO)
TX-SR806/SA806
Digital Input Port Clocks
I/O
I/O
I/O
I/O
Digital input port Clock 0.
Digital input port Clock 1.
Digital input port Clock 2.
Digital input port Clock 3.
IPCLK0
IPCLK1
IPCLK2
IPCLK3
N1
P4
M4
L1
Digital A Input Port
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
Digital input port A VSync.
Digital input port A HSync.
Digital input port A Data Enable.
Digital input port A channel odd input.
Digital input port H Sync or CSync input.
Digital input port clamp output.
Digital input port coast output.
Digital input port HSync out.
Digital input port A bit 23.
Digital input port A bit 22.
Digital input port A bit 21.
AVS
AHS
AHREF_DE
DIP_AODD
DIP_RAW_HS_CS
DIP_EXT_CLAMP
DIP_EXT_COAST
DIP_CLEAN_HS_OUT
ADATA23
ADATA22
ADATA21
Y1
Y2
Y3
N3
N2
M2
M3
M1
Y4
W1
W2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Pin name Pin# I/O Description
Pin name Pin# I/O Description