TERMINAL DESCRIPTION(9/10)
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -51
Q8200: FLI30336 (Video Processor, TORINO)
TX-SR806/SA806
Frame Store DDR Interface
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
AP
AG
P
A8
B8
A7
B7
A5
B5
A4
B4
B22
B17
A11
A6
C20
C21
C11
C14
D16
C12
C6
C7
C8
C10
C13
C15
C16
C17
C18
D21
C22
A14
B14
D4,D6,
D7,D8,
D10,D11,
D12,D13,
D14,D15,
D17,D18,
D20,D22,
D23
Data input/output. Synchronized with FSDQS0. SSTL2
Data input/output. Synchronized with FSDQS0. SSTL2
Data input/output. Synchronized with FSDQS0. SSTL2
Data input/output. Synchronized with FSDQS0. SSTL2
Data input/output. Synchronized with FSDQS0. SSTL2
Data input/output. Synchronized with FSDQS0. SSTL2
Data input/output. Synchronized with FSDQS0. SSTL2
Data input/output. Synchronized with FSDQS0. SSTL2
Data out mask. Only used during write cycles.
Data out mask. Only used during write cycles.
Data out mask. Only used during write cycles.
Data out mask. Only used during write cycles.
Bank select address.
Bank select address. Row/column address outputs multiplexed on to the same pins.
Bank select address. Row/column address outputs multiplexed on to the same pins.
Bank select address. Row/column address outputs multiplexed on to the same pins.
Bank select address. Row/column address outputs multiplexed on to the same pins.
Bank select address. Row/column address outputs multiplexed on to the same pins.
Bank select address. Row/column address outputs multiplexed on to the same pins.
Bank select address. Row/column address outputs multiplexed on to the same pins.
Bank select address. Row/column address outputs multiplexed on to the same pins.
Bank select address. Row/column address outputs multiplexed on to the same pins.
Bank select address. Row/column address outputs multiplexed on to the same pins.
Bank select address. Row/column address outputs multiplexed on to the same pins.
Bank select address. Row/column address outputs multiplexed on to the same pins.
Bank select address. Row/column address outputs multiplexed on to the same pins.
Bank select address. Row/column address outputs multiplexed on to the same pins.
Chip select 0 pin(ball). SSTL2
Chip select 1 pin(ball). SSTL2
1.8V power supply for on chip DLL for DDR interface timing control.
Power supply return for on chip DLL.
2.5V power supply for DDR SSTL2 I/O’s.
FSDATA7
FSDATA6
FSDATA5
FSDATA4
FSDATA3
FSDATA2
FSDATA1
FSDATA0
FSDQM3
FSDQM2
FSDQM1
FSDQM0
FSBKSEL1
FSBKSEL0
FSADDR12
FSADDR11
FSADDR10
FSADDR9
FSADDR8
FSADDR7
FSADDR6
FSADDR5
FSADDR4
FSADDR3
FSADDR2
FSADDR1
FSADDR0
FSCS0
FSCS1
VDDA18_DLL
VSSA18_DLL
DDR2.5
Pin name Pin# I/O Description
