Q8000, Q8001: HY5DU561622ETP (256 Mbit DDR SDRAM)
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -54
TX-SR806/SA806
BLOCK DIAGRAM
PIN CONFIGURATION
Command
Decoder
Bank
Control
Mode
Register
Row
Decoder
4Mx16 / Bank0
4Mx16 / Bank1
4Mx16 / Bank2
4Mx16 / Bank3
Write Data Register
2-bit Prefetch Unit
2-bit Pref
etch Unit
Sense Amp
Output Buff
er
Input Buff
er
32
32
16
16
LDQS, UDQS
LDQS, UDQS
LDQS
UDQS
LDM, UDM
DQ[0:15]
Data Strobe
Transmitter
Data Strobe
Receiver
Column Decoder
Column Address
Counter
Mode
Register
DLL
Block
CLK_DLL
CLK,
/CLK
Address
Buffer
ADD
BA
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
66 pin TSOP
Top View