NCN49597
http://onsemi.com
20
XTAL_IN
PC20111118.1
XTAL_OUT
C
X
V
SSA
C
X
48 MHz
Figure 13. Placement of the Capacitors and Crystal
with Clock Signal Generated Internally
For correct functionality the external circuit illustrated in
Figure 13 must be connected to the oscillator pins. For a
crystal requiring a parallel capacitance of 18 pF C
X
must be
around 36 pF. (Values of capacitors are indicative only and
are given by the crystal manufacturer). To guarantee startup
the series loss resistance of the crystal must be smaller than
60
W
.
The oscillator output f
CLK
= 48 MHz is the base frequency
for the complete IC. The clock frequency for the ARM f
ARM
= f
CLK.
The clock for the transmitter, f
TX_CLK
is equal to
f
CLK
/ 4 or 12 MHz. All the transmitter internal clock signals
will be derived from f
TX_CLK
. The clock for the receiver,
f
RX_CLK
is equal to f
CLK
/ 8 or 6 MHz. All the receiver
internal clock signals will be derived from f
RX_CLK.
Clock Generator and Timer
The CHIP_CLK and f
CLK
are used to generate a number
of timing signals used for the synchronization and interrupt
generation. The timing generation has a fixed repetition rate
which corresponds to the length of a physical subframe. (see
paragraph
Error! Reference source not found.
)
The timing generator is the same for transmit and receive
mode. When NCN49597 switches from receive to transmit
and back from transmit to receive, the R_CHIP_CNT
counter value is maintained. As a result all timing signals for
receive and transmit have the same relative timing. The
following timing signals are defined as:
BIT_CLK
63
64
65
2871 2872
1
0
2879
2
3
4
5
6
7
8
9
CHIP_CLK
BYTE_CLK
FRAME_CLK
PRE_FRAME_CLK
PRE_BYTE_CLK
R_CHIP_CNT
PRE_SLOT
PC20090619.1
Start of the physical subframe
Figure 14. Timing Signals
CHIP_CLK
: is the output of the PLL and 8 times the bit rate
on the physical interface. See also paragraph
50/60 Hz PLL
.
BIT_CLK: is active at counter values 0, 8, 16, .. 2872 and
inactive at all other counter values. This signal is used to
indicate the transmission of a new bit.
BYTE_CLK
: is active at counter values 0, 64, 128, .. 2816
and inactive at all other counter values. This signal is used
to indicate the transmission of a new byte.
