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NCN49597

http://onsemi.com

18

t

10 ms

V

MAINS

ZeroCross

t

ZCD

VIR

ZC_IN

PC20090620 .1

VIF

ZC_IN

t

DEBOUNCE

= 0,5 .. 1 ms

Figure 11. Zero Cross Detector Signals and Timing (example for 50 Hz)

50/60 Hz PLL

The output of the zero cross detector is used as an input for

a PLL. The PLL generates the clock CHIP_CLK which is 8
times the bit rate and which is in phase with the rising edge

crossings. The PLL locks on the zero cross from negative to
positive phase. The bit rate is always an even multiple of the
mains frequency, so following combinations are possible:

Table 18. CHIP_CLK IN FUNCTION OF SELECTED BAUD RATE AND MAINS FREQUENCY

BAUD[1:0]

MAINS_FREQ

Baudrate

CHIP_CLK

00

50 Hz

300

2400 Hz

01

600

4800 Hz

10

1200

9600 Hz

11

2400

19200 Hz

00

60 Hz

360

2880 Hz

01

720

5760 Hz

10

1440

11520 Hz

11

2880

23040 Hz

In case no zero crossings are detected the PLL freezes its internal timers in order to maintain the CHIP_CLK timing.

Содержание NCN49597

Страница 1: ...ble Carrier Frequencies in CENELEC A Band from 9 to 95 kHz B Band from 95 to 125 kHz in 10 Hz Steps Half Duplex Data Rate Selectable 300 600 1200 2400 4800 baud 50 Hz 360 720 1440 2880 5760 baud 60 Hz...

Страница 2: ...it path a 3th order low pass filter build around the NCS5650 power operational amplifier suppresses the 2nd and 3rd harmonics to be in line with the CENELEC EN 50065 1 specification The filter compone...

Страница 3: ...ng Symbol Min Max Unit ABSOLUTE MAXIMUM RATINGS SUPPLY Power Supply Pins VDD VDDA VSS VSSA Absolute max digital power supply VDD_ABSM VSS 0 3 3 9 V Absolute max analog power supply VDDA_ABSM VSSA 0 3...

Страница 4: ...IS49597 1 2 3 4 5 6 7 8 9 10 11 12 13 26 25 24 23 22 21 20 19 18 17 16 15 14 39 38 37 36 35 34 33 32 31 30 29 28 27 40 41 42 43 44 45 46 47 48 49 50 51 52 NC REF_OUT NC RX_IN RX_OUT VSSA VDDA NC NC AL...

Страница 5: ...In D Hardware Test enable internal pull down 37 TX_ENB Out D 5V Safe TX enable bar open drain 42 TX_OUT Out A Transmitter output 43 ALC_IN In A Automatic level control input 46 VDDA P 3 3V analog sup...

Страница 6: ...In case of direct connection to the mains it is advised to use a series resistor of 1 MW in combination with two external clamp diodes in order to limit the current flowing through the internal prote...

Страница 7: ...0 and BR1 are 5 V safe CRC CRC is a 5 V compliant open drain output An external pull up resistor defines the logic high level as illustrated in Figure 4 A typical value for this pull up resistance R i...

Страница 8: ...OSCILLATOR Parameter Test Conditions Symbol Min Typ Max Unit Crystal frequency Note 1 fCLK 100 ppm 48 100 ppm MHz Duty cycle with quartz connected Note 1 40 60 Start up time Note 1 Tstartup 50 ms Load...

Страница 9: ...0 4 V Lock range for 50 Hz Note 3 MAINS_FREQ 0 50 Hz Flock50Hz 45 55 Hz Lock range for 60 Hz Note 3 MAINS_FREQ 0 60 Hz Flock60Hz 54 66 Hz Lock time Note 3 MAINS_FREQ 0 50 Hz Tlock50Hz 15 s Lock time N...

Страница 10: ...N pin RALC_IN 111 189 kW Power supply rejection ration of the transmitter section PSRRTX_OUT 10 Note 7 35 Note 8 dB 4 This parameter will not be tested in production 5 This delay corresponds to the in...

Страница 11: ...lipping level at the output of the gain stage RX_OUT VCLIP_AGC_IN 1 15 1 65 Vp 9 Input at RX_IN no other external components 10 Characterization data only Not tested in production 11 A sinusoidal sign...

Страница 12: ...mA VOL 0 4 V Digital Inputs BR0 BR1 Table 14 DIGITAL INPUTS BR0 BR1 Parameter Test Conditions Symbol Min Typ Max Unit Low input level VIL 0 2 VDD V High input level 0 to 3 V VIH 0 8 VDD V Input leaka...

Страница 13: ...ndent at the two frequencies The frequency pairs supported by the NCN49597 are in the range of 9 150 kHz with a typical separation of 10 kHz The conditioning and conversion of the signal is performed...

Страница 14: ...ter is a client to the data served by one or many slaves on the power line It collects data from and controls the slave devices A typical application is a concentrator system Slave or Server A Slave i...

Страница 15: ...n Then the level of the signal is automatically adapted by an automatic gain control AGC block This operation maximizes the dynamic range of the incoming signal The signal is then converted to its dig...

Страница 16: ...eceiving is in progress or if NCN49597 is waiting for synchronization or of it configures CRC indicates if the received frames are valid CRC OK TXD PRES is the output for either the transmitting data...

Страница 17: ...ection to the mains it is advised to use a series resistor of 1 MW in combination with two external Schottky clamp diodes in order to limit the current flowing through the internal protection diodes F...

Страница 18: ...rising edge crossings The PLL locks on the zero cross from negative to positive phase The bit rate is always an even multiple of the mains frequency so following combinations are possible Table 18 CH...

Страница 19: ...ay tZCD e g opto coupler and for the 1 9 V positive threshold VIRZC_IN of the zero cross detector This is done by pre loading the PLL counter with a number value stored in register R_ZC_ADJUST 7 0 The...

Страница 20: ...generate a number of timing signals used for the synchronization and interrupt generation The timing generation has a fixed repetition rate which corresponds to the length of a physical subframe see p...

Страница 21: ...high frequency quantization noise and passed to the automatic level controller ALC block where the level of the transmitted signal can be adjusted The determination of the signal level is done throug...

Страница 22: ...A goes to logic 1 at the next BIT_CLK PC20090610 1 TX_DATA TX_RXB tdTX_ENB BIT_CLK TX_ENB TX_OUT Figure 16 TX_ENB Timing DA Converter A digital to analog SD converter converts the sine wave digital wo...

Страница 23: ...igure 17 a MFB topology of a 2nd order filter is illustrated ALC control ALC_IN Transmitter S FSK Modulator PC 20091216 1 ARM Interface Control TX_OUT LP Filter TX_EN TO TX POWER OUTPUT STAGE FROM LIN...

Страница 24: ...fier REF_OUT is the analog output pin which provides the voltage reference 1 65 V used by the A D converter This pin must be decoupled from the analog ground by a 1 mF ceramic capacitance CDREF It is...

Страница 25: ...asurement cycle at the rising edge of the CHIP_CLK and an update cycle starting at the next CHIP_CLK Low Noise Anti Aliasing Filter The receiver has a 3rd order continuous time low pass filter in the...

Страница 26: ...tart of the Demodulating Process The synchro bit value can be set using register SBV 2 0 Table 23 SYNCHRO BIT VALUE SBV 2 0 Bit Delay 000 0 CHIP_CLK 001 1 CHIP_CLK 010 2 CHIP_CLK 011 3 CHIP_CLK 100 4...

Страница 27: ...L version V1 0 Linky PLC profile functional specification http www erdfdistribution fr medias Linky ERD F CPT Linky SPEC FONC CPL pdf 4 DLMS UA 1000 2 Ed 7 0 DLMS COSEM Architecture and Protocols http...

Страница 28: ...application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as comp...

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