Omega PCI-DAS1602/16, Руководство пользователя, Страница: 26 / 39

READ
LDAEM
- - - - - - - - - - - - - - -
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LDAEM
This is the latched version of the DAC FIFO_EMPTY signal. This bit must be write-write
cleared with the DAEMCL bit.
1 = DAC FIFO was emptied at some point during FIFO'd operations. Incorrect data may have
been clocked into the selected DAC(s).
0 = DAC FIFO did not empty during FIFO'd operations. Status good.
8.3 BADR2
The I/O Region defined by BADR2 contains the ADC Data register and the ADC FIFO clear
register.
8.3.1 ADC Data Register
BADR2 + 0 ADC Data register.
WRITE
Writing to this register is only valid for SW initiated conversions. The ADC Pacer source must
be set to 00 via the ADPS[1:0] bits. A null write to BADR2 + 0 with begin a single conversion.
Conversion status may be determined in two ways. The EOC bit in BADR1 + 0 may be polled
until true or ADNEI (the AD FIFO not-empty interrupt) may be used to signal that the ADC
conversion is complete and the data word is present in the FIFO.
READ
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MSB LSB
AD[15:0]
This register contains the current ADC data word. Data format is dependent upon offset mode:
Bipolar Mode: Offset Binary Coding
0000 h = -FS
7FFFh = Mid-scale (0V)
FFFFh = +FS - 1LSB
Unipolar Mode: Straight Binary Coding
0000 h = -FS (0V)
7FFFh = Mid-scale (+FS/2)
FFFFh = +FS - 1LSB
8.3.2 ADC FIFO Clear Register
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