Omega PCI-DAS1602/16, Руководство пользователя, Страница: 16 / 39

DAEMCL
A write-clear to reset DAEM interrupt status.
1= Clear DAEM interrupt. 0 = No effect.
NOTE: It is not necessary to reset any write-clear bits after they are set.
READ
- - - - - DAHFI EOAI INT XINTI EOBI ADHFI ADNEI ADNE LADFUL DAEMI -
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Write operations to this register allow you to check status of the selected interrupts and ADC
FIFO flags. The following is a description of Interrupt / ADC FIFO Register Read bits:
DAHFI
Status bit of DAC FIFO Half-Full interrupt
1 = Indicates a DAC FIFO Half-Full interrupt has been latched. 0 = Indicates a DAHF interrupt
has not occurred.
EOAI
Status bit of ADC FIFO End-of-Acquisition interrupt.
1 = Indicates an EOA interrupt has been latched. 0 = Indicates an EOA interrupt has not
occurred.
INT
Status bit of General interrupt selected via INT[1:0] bits. This bit indicates that any one of these
interrupts has occurred.
1 = Indicates a General interrupt has been latched. 0 = Indicates a General interrupt has not
occurred.
XINTI
Status bit of External interrupt. External interrupt requires a rising TTL logic level input.
1 = Indicates an External interrupt has been latched. 0 = Indicates an interrupt has not occurred.
EOBI
Status bit ADC End-of-Burst interrupt. Only valid for ADC Burst Mode enabled.
1 = Indicates an EOB interrupt has been latched. 0 = Indicates an EOB interrupt has not
occurred.
ADHFI
Status bit of ADC FIFO Half-Full interrupt. Used during REP INSW operations.
1 = Indicates an ADC Half-Full interrupt has been latched. FIFO has been filled with more than
255 samples. 0 = Indicates an ADC Half-Full interrupt has not occurred. FIFO has not yet
exceeded 1/2 of its total capacity.
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