Omega PCI-DAS1602/16 Скачать руководство пользователя страница 21 | Manualshive

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Omega PCI-DAS1602/16 Скачать руководство пользователя страница 21

Note that the CHI Threshold is set by DAC1, CLO Threshold is set by DAC0.
HMODE
CHI >= CLO by definition.

Window

Signal goes high when within region defined by

CHI-CLO. Signal is low outside this region.

X

1

1

Positive

Slope

Signal goes high when ATRIG is more positive than

CHI.

CLO has no effect.

X

0

1

Negative

Slope

Signal goes high when ATRIG more negative than

CLO.

CHI has no effect.

X

1

0

Positive

Hysteresis

Signal goes HIGH when ATRIG is more negative than

CLO. Signal goes low when ATRIG becomes more
positive than CHI. Hysteresis level is the difference

between CHI and CLO.

1

0

0

Negative

Hysteresis

Signal goes HIGH when ATRIG is more positive than

CHI. Signal goes low when ATRIG becomes more

negative than CLO. Hysteresis level is the difference

between CHI and CLO.

0

0

0

Mode

Analog Trigger/Gate Function

HMODE

CLO_EN

CHI_EN

ARM, FFM0

These bits work in conjunction the PRTRG bit during FIFO'd ADC operations. Note that
1 FIFO = 512 samples.

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Содержание PCI-DAS1602/16

Страница 1: ...User s Guide http www omega com e mail info omega com PCI DAS1602 16...

Страница 2: ...O Register Page 13 8 2 BADR1 Page 13 8 1 BADR0 Page 13 8 0 PCI DAS1602 16 REGISTER DESCRIPTION Page 12 7 2 Analog Output Calibration Page 11 7 1 Analog Input Calibration Page 11 7 0 SELF CALIBRATION O...

Страница 3: ...ith your board insert the Universal Library diskette or CD in an appropriate drive run the program SETUP EXE and follow the installation instructions provided This program will install both InstaCalTM...

Страница 4: ...setup wizard will automatically install the 16 bit version of the Universal Library and InstaCAL These versions are compatible with the DOS operating system If you need to install the software and do...

Страница 5: ...ectory 3 3 Base I O Address Interrupt Level The PCI DAS1602 16 uses a number of addresses and one interrupt The addresses are allocated by the PCI plug play procedure and may not be modified If you ha...

Страница 6: ...ollowing section describes the InstaCal procedure to test that your board is properly installed The procedure has you connect one of the outout channels to one of the A D channels it then outputs a si...

Страница 7: ...Ch 2 Low 10 High Analog Input Ch 3 High Analog Input Ch 3 Low 11 High Analog Input Ch 4 High Analog Input Ch 4 Low 12 High Analog Input Ch 5 High Analog Input Ch 5 Low 13 High Analog Input Ch 6High An...

Страница 8: ...30 volts will likely damage the board and possibly the computer 4 3 Analog Input Configurations SINGLE ENDED Single ended inputs are most appropriate in systems where the signal source and the data ac...

Страница 9: ...l source it s probably not floating DIFFERENTIAL Proper measurement of a differential signal requires three wires from the signal source The signals are Signal High CH HI Signal Low CH LO and Signal G...

Страница 10: ...iew The PCI DAS1602 16 is a multifunction measurement and control board The design of the board may be simplified into several blocks containg the major functions of the board Please take a moment to...

Страница 11: ...ased on a DLL interface to Windows languages A set of VBX OCX or ActiveX interfaces allows point and click construction of graphical displays analysis and control structures Please see the catalog for...

Страница 12: ...res no user intervention 7 1 Analog Input Calibration A variety of methods are used to calibrate the different elements on the board The analog front end has several knobs to turn Offset calibration i...

Страница 13: ...in Adj Trim Dac Trim Dac Coarse Coarse Trim Dac Trim Dac Fine Fine Trim Dac Trim Dac Coarse Coarse Trim Dac Trim Dac Fine Fine Trim Dac Trim Dac Coarse Coarse Trim Dac Trim Dac Fine Fine Gain Adj Trim...

Страница 14: ...aranteed to be the same even on subsequent power on cycles of the same machine All software must interrogate BADR0 at run time with a READ_CONFIGURA TION_DWORD instruction to determine the BADRn value...

Страница 15: ...t Used during FIFO d ADC operations to indicate that the desired sample size has been gathered 1 Enable EOA interrupt 0 Disable EOA interrupt DAHFCL A write clear to reset DAC FIFO Half Full interrupt...

Страница 16: ...nterrupt has not occurred INT Status bit of General interrupt selected via INT 1 0 bits This bit indicates that any one of these interrupts has occurred 1 Indicates a General interrupt has been latche...

Страница 17: ...ADC FIFO DAEMI Status bit of DAC FIFO Empty interrupt Used to indicate that a FIFO d DAC Operation has completed 1 DAC FIFO Empty interrupt condition has occurred 0 DAC FIFO Empty interrupt condi tion...

Страница 18: ...selected range 0 Analog Front End Bipolar for selected range The following table summarizes all possible Offset Range configurations 19uV 8 0 1 25V 1 1 1 38uV 4 0 2 5V 0 1 1 76uV 2 0 5V 1 0 1 153uV 1...

Страница 19: ...CLO_EN CHI_EN HMODE ARM FFM0 C0SRC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TS 1 0 These bits select one of three possible ADC Trigger Sources External Analog 1 1 External Digital 0 1 SW Trigger 1 0 Dis...

Страница 20: ...edge TGSEL 1 Edge Triggered event TGEN 1 Enable External Trigger Once TGEN is set the next falling edge will start a Paced ADC conversion Subsequent triggers will have no effect until external trigge...

Страница 21: ...effect X 1 0 Positive Hysteresis Signal goes HIGH when ATRIG is more negative than CLO Signal goes low when ATRIG becomes more positive than CHI Hysteresis level is the difference between CHI and CLO...

Страница 22: ...iately 0 0 Sample CTR Starts on FIFO Mode ARM is set FFM0 PRTRG C0SRC This bit allows the user to select the clock source for user Counter 0 1 Internal 10MHz oscillator 0 External clock source input v...

Страница 23: ...it trim DACs for the following circuits DAC1 Fine Offset 7 DAC0 Fine Offset 6 DAC1 Coarse Gain 5 DAC1 Fine Gain 4 DAC1 Offset 3 DAC0 Offset 2 DAC0 Coarse Gain 1 DAC0 Fine Gain 0 Cal Function DAC Chann...

Страница 24: ...ed to set serial address data stream for the DAC8800 TrimDac and 8402 digital potentiometer Used in conjunction with SEL8800 and SEL8402 bits 8 2 5 DAC Control Status Register BADR1 8 This register se...

Страница 25: ...C Pacer Source External Rising Edge 1 1 External Falling Edge 0 1 Internal 82C54 Programmed via BADR3 9 A 1 0 SW Convert 0 0 Pacer Source DAPS0 DAPS1 HS 1 0 These bits select the High Speed DAC Modes...

Страница 26: ...sions The ADC Pacer source must be set to 00 via the ADPS 1 0 bits A null write to BADR2 0 with begin a single conversion Conversion status may be determined in two ways The EOC bit in BADR1 0 may be...

Страница 27: ...ndex UserCounter 0 8254B ADC Pacer Upper Divider 2 8254A ADC Pacer Lower Divider 1 8254A ADC Post Trigger Sample Counter 0 8254A Function Counter Device All reads writes to BADR3 are byte operations 8...

Страница 28: ...unt written to the specific Counter Register The Counters on the 8254 are 16 bit devices Since the interface to the 8254 is only 8 bits wide Count data is written to the Counter Register as two succes...

Страница 29: ...it may be split every write to Port C is a byte operation Unwanted information must be ANDed out during reads and writes must be ORd with current value of the other 4 bit port READ WRITE D0 D1 D2 D3 D...

Страница 30: ...ADC PRE TRIGGER INDEX COUNTER BADR3 8 READ WRITE D0 D1 D2 D3 D4 D5 D6 D7 0 1 3 2 4 5 6 7 Counter 0 of the DAC 8254 device is actually used as the ADC Pre Trigger index counter This counter serves to m...

Страница 31: ...1 D2 D3 D4 D5 D6 D7 0 1 3 2 4 5 6 7 The control register is used to set the operating Modes of 8254 Counters 0 1 2 A counter is configured by writing the correct Mode information to the Control Regist...

Страница 32: ...e that the FIFO be loaded with the appropriate data A REP OUTSW instruction to this address will do this It is important to note that the FIFO is the shared data source between DAC0 and DAC1 Care must...

Страница 33: ...FO Clear Register BADR4 2 DAC FIFO Clear register A Write only register A write to this address location clears the DAC FIFO Data is don t care The DAC FIFO should be cleared before all new DAC operat...

Страница 34: ...arity error Unipolar 2 1 5 LSB Gain Error 10V 0 10V Ranges 22 5ppm Max 5V 0 5V Ranges 22 5ppm Max 2 5V 0 2 5V Ranges 22 5ppm Max 1 25 V 0 1 25V Ranges 22 5ppm typical 45ppm Max No missing codes guaran...

Страница 35: ...Ranges 3V uS D A trigger modes SW or external gate Current Drive 5 mA min Output short circuit duration 25 mA indefinite Miscellaneous Double buffered input latches Update DACs individually or simult...

Страница 36: ...Mode User counter 4 Source User input at 100pin connector or internal 10MHz software selectable Gate User input at 100pin connector Output Available at 100pin connector Counter 1 DAC Pacer Lower Divid...

Страница 37: ...For Your Notes Page 36...

Страница 38: ...Essential requirements relating to electromagnetic compatibility EU 55022 Class B Limits and methods of measurements of radio interference characteristics of information technology equipment EN 50082...

Страница 39: ......

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