![Oki ML670100 Скачать руководство пользователя страница 74](http://html1.mh-extra.com/html/oki/ml670100/ml670100_user-manual_4174189074.webp)
Chapter 4 User Interface
Page4-7
Table 4.3. CNUA Pin Assignments
CNU1No.
Pin Name
I/O
CNU2No.
Pin Name
I/O
1
AI4
I
41
XA2
O
2
AI3
I
42
XA3
O
3
AI2
I
43
XA4
O
4
AI1
I
44
XA5
O
5
AI0
I
45
XA6
O
6
VREF
I
46
XA7
O
7
N.C.
-
47
GND
O
8
VDD
I
48
VDD
I
9
N.C.
-
49
XA8
O
10
DBSEL
*1
I
50
XA9
O
11
PIO6.0
I/O
51
XA10
O
12
PIO6.1
I/O
52
XA11
O
13
PIO6.2
I/O
53
XA12
O
14
PIO6.3
I/O
54
XA13
O
15
PIO6.4
I/O
55
XA14
O
16
PIO6.5
I/O
56
XA15
O
17
PIO6.6
I/O
57
GND
O
18
PIO6.7
I/O
58
VDD
I
19
PIO7.0
I/O
59
PIO0.0
*3
I/O
20
PIO7.1
I/O
60
PIO0.1
*3
I/O
21
PIO7.2
I/O
61
PIO0.2
*3
I/O
22
GND
O
62
PIO0.3
*3
I/O
23
VDD
I
63
PIO0.4
*3
I/O
24
PIO7.3
I/O
64
PIO0.5
*3
I/O
25
PIO7.4
I/O
65
PIO0.6
*3
I/O
26
PIO7.5
I/O
66
PIO0.7
*3
I/O
27
PIO7.6
I/O
67
EFIQ/
I
28
PIO7.7
I/O
68
EA/
*4
I
29
PIO8.0
*2
I/O
69
GND
O
30
PIO8.1
*2
I/O
70
VDD
I
31
PIO8.2
*2
I/O
71
XD0
I/O
32
PIO8.3
*2
I/O
72
XD1
I/O
33
PIO8.4
*2
I/O
73
N.C.
-
34
PIO8.5
*2
I/O
74
N.C.
-
35
PIO8.6
*2
I/O
75
N.C.
-
36
PIO8.7
*2
I/O
76
N.C.
-
37
GND
O
77
GND
O
38
VDD
I
78
GND
O
39
XA0
O
79
GND
O
40
XA1
O
80
GND
O
*1
This pin has a 100-k
Ω
pull-up resistance.
*2
The NORMAL position of the MODE switch disconnects all but one of these pins. It adds a
10-k
Ω
pull-up resistance to the PIO8.2 pin.
*3
These pins are used for their secondary functions, so are not available for use as port pins.
*4
This pin has a 100-k
Ω
pull-down resistance.
Содержание ML670100
Страница 16: ...Chapter 1 Read Me First Page 1 12...
Страница 79: ...Chapter 4 User Interface Page4 12...
Страница 91: ...Chapter 5 Notes on Debugging Page 5 12...
Страница 92: ...Chapter 6 Appendices...