Chapter 3 Setup and Operation
Page 3-11
Figure 3.12. Memory Mask Jumpers (J1 to J4) Circuits
+3.3V
1
3
J3
xx_nWRE
xx_nRD
SRAM_nWE0
(0x00000000 to 0x0007FFFF)
SRAM_nOE0
(0x00000000 to 0x0007FFFF)
xx_nWRE
xx_nRD
FLASH_nWE0
(0x00800000 to 0x0081FFFF)
FLASH_nOE0
(0x00800000 to 0x0081FFFF)
xx_nWRE
xx_nRD
FLASH_nWE1
(0x00820000 to 0x0083FFFF)
FLSAH_nOE1
(0x00820000 to 0x0083FFFF)
+3.3V
1
3
J1
+3.3V
1
3
J2
P0.0/XA16
+3.3V
1
3
J4
xx_nWRE
xx_nRD
SRAM_nWE1
(0x00100000 to 0x0017FFFF)
SRAM_nOE1
(0x00100000 to 0x0017FFFF)
Содержание ML670100
Страница 16: ...Chapter 1 Read Me First Page 1 12...
Страница 79: ...Chapter 4 User Interface Page4 12...
Страница 91: ...Chapter 5 Notes on Debugging Page 5 12...
Страница 92: ...Chapter 6 Appendices...