Oki ML670100, Руководство пользователя

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Chapter 4 User Interface
Page4-2
4.1 Overview
The evaluation chip on the Oki ML670100 CPU Board features the same memory spaces,
peripherals, and I/O pins (See Note 1) as the target ML670100.
Connecting the I/O pins available on the Oki ML670100 CPU Board to the user application
system with the user interface connectors and optional user cable permits in-place
debugging.
Figure 4.1 outlines this relationship.
Figure 4.1. User Interface Equivalence
! ! ! ! Note 1 ! ! ! !
The Oki ML670100 CPU Board sometimes handles the following ML670100 built-in
peripheral ports and pins differently: PIO0, PIO1, PIO2.5, PIO2.6, PIO5.6, PIO5.7, and PIO8.
For further details, see Chapter 5 "Notes on Debugging."
External address bus
External ddress bus
ML670100
Emulation memory
User interface connectors
JTAG communications interface connector
ML670100 CPU BOARD
RS232C-interface connector
Debugging interface
Serial interface
ML670100-compatible I/O pin