96
Count the number of flashes; the resulting number matches the POST error found
in the Table 16–2. For example, five flashes indicates the CPU test failed.
The POST codes are listed in numerical order. This is not the sequence in which
the actions are executed.
Table 16–1 POST port 80 codes
Port 80
Code
POST Routine Description
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
OEh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
Start POST (BIOS is executing)
Start CPU register test
Start power-on delay
Power-on delay finished
Keyboard BAT finished
Disable shadowing and cache
Compute ROM CRC, wait for KBC
CRC okay, KBC ready
Verifying BAT command to KB
Start KBC command
Start KBC data
Start pin 23, 24 blocking and unblocking
Start KBC NOP command
Test CMOS RAM shutdown register
Check CMOS checksum
Initialize CMOC contents
Initialize CMOS status for date/time
Disable DMA, PICs
Disable Port B, video display
Initialize board, start memory detection
Start timer tests
Test 8254 T2, for speaker, Port B
Test 8254 T1, for refresh
Test 8254 T0, for 18.2 Hz
Start memory refresh
Test memory refresh
Test 15 sec ON/OFF time
Test base 64KB memory
Test data lines
Test address lines
Test parity (toggling)
Test Base 64KB memory
Prepare system for IVT initialization
Initialize vector table
Read 8042 for turbo switch setting
Initialize turbo data
Modification of IVT
Video in monochrome verified
Video in color mode verified
Toggle parity before video ROM test
Initialize before video ROM test
Passing control to video ROM
Содержание XE-900
Страница 19: ...19 Figure 2 1 XE 900 SBC component diagram top ...
Страница 20: ...20 Figure 2 2 XE 900 SBC component diagram bottom ...
Страница 21: ...21 Figure 2 3 XE 900 SBC dimensions without Integrated Conductive Cooling System ...
Страница 38: ...38 ...
Страница 91: ...91 Figure 15 2 Dimensions for the Integrated Conductive Cooling System ...