NXP Semiconductors S32K3X4EVB-Q257, Руководство пользователя по оборудованию, Страница: 29 / 36

NXP Semiconductors
S32K3X4EVB-Q257 | S32K3X4EVBQ257ND HWUM
Hardware User Manual
S32K3X4EVB-Q257 HWUM All Information provided in this document is subject to legal disclaimers © NXP B.V. 2020. All rights reserved
NXP Semiconductors REV B
– 9/2021
Page 29 of 36
The table below details the signals configuration for the QSPI-A.
Module
/Function
Signal
MCU
PORT
DESCRIPTION /COMMENT
QSPIA QSPI_A_IO0_MCU PTD11 All MCU ports routed to the QSPIA Memory Interface are not
connected to other interface in the EVB.
QSPI_A_IO1_MCU PTD7
QSPI_A_IO2_MCU PTD12
QSPI_A_IO3_MCU PTC2
QSPI_A_SCK_MCU PTD10
QSPI_A_CS_MCU PTC3
15 User Peripherals
15.1 GPIO Matrix
A subset of available GPIO pins (available pins being those not already routed to the Ethernet connector and the QSPIA-Memory
Interface) are available at the GPIO matrix as detailed below. The matrix provides an easy to follow, intuitive, space-saving grid o
f 0.1”
header through-hole pads. Users can solder wires, fit headers, or simply insert a scope probe into the respective pad.
Figure 26. S32K3X4EVB-Q257 | S32K3X4EVBQ257ND
– GPIO Matrix
Figure 27. S32K3X4EVB-Q257 | S32K3X4EVBQ257ND
– GPIO Matrix