NXP Semiconductors
UM11802
RDGD3162I3PH5EVB three-phase inverter reference design
Test point name
Function
GLU
gate low-side U phase which is the charging pin of IGBT gate
GLV
gate low-side V phase which is the charging pin of IGBT gate
GLW
gate low-side W phase which is the charging pin of IGBT gate
INTA – UVW HS and LS
INTA interrupt/real-time reporting output signal test points from each gate driver
Resolver circuit
test points for internal signals of resolver circuit (see schematic for more information)
MCU signals
signal headers for analyzing all MCU signals (see schematic for signals)
TSNSHU
TSENSE high-side U phase connected to negative temperature coefficient (NTC) temperature
sense
TSNSLU
TSENSE low-side U phase
VREFLU
5.0 V reference voltage test point low-side U phase
VREFHU
5.0 V reference voltage test point high-side U phase
VREFLV
5.0 V reference voltage test point low-side V phase
VREFHV
5.0 V reference voltage test point high-side V phase
VREFLW
5.0 V reference voltage test point low-side W phase
VREFHW
5.0 V reference voltage test point high-side W phase
VSUP
VSUP/VPWR test point low-voltage domain
Table 2. Test points
...continued
UM11802
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2022. All rights reserved.
User manual
Rev. 1 — 10 June 2022
12 / 38