NXP Semiconductors QN902 Series, Руководство пользователя

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NXP Semiconductors
QN902x
User Manual of QN902x
UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
User Manual Rev 1.3
— 05 November 2018
86 of 128
11.4.2 Register Description
Table 61 TCR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
R
SVD
R
SVD
C
SS
[1]
C
SS
[0]
R
SVD
R
SVD
PS
C
L[9]
PS
C
L[8]
PS
C
L[7]
PS
C
L[6]
PS
C
L[5]
PS
C
L[4]
PS
C
L[3]
PS
C
L[2]
PS
C
L[1]
PS
C
L[0]
PWM_O
E
PO
L
ICN
C
E
ICS
S
ICP
S[1]
ICP
S[0]
ICE
S[1]
ICE
S[0]
ICC
LR
C
HAIN_
EN
O
M
S[1]
O
M
S[0]
ICIE
O
C
IE
TO
VI
E
TEN
0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R R
RW RW
R R
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Type Reset Symbol Description
31-30 R 0 RSVD Reserved
29-28 RW 10b CSS
clock sources selection
00b = external input clock;
01b = reserved.
10b, 11b = Clk_timer prescaler clock.
27-26 R 0 RSVD Reserved
25-16 RW 3FFh PSCL
prescaler factor
CLK_SCALED = CLK_TIMER/ (PSCL + 1)
Note: when pscl equals to zero, it means non scale.
15 R 0 PWM_OE
PWM output enable
0 = disable;
1 = enable.
14 RW 0 POL
PWM output polarity control.
0 = Set high on compare match, set low at the end of PWM
period;
1 = Set low on compare match, set high at the end of PWM
period.
13 RW 0 ICNCE
Input capture noise canceller enable:
0 = disable;
1 = enable.
12 RW 0 ICSS
Input capture source select:
0 = ICP, input capture pin;
1 = ACMP, Analog comparator output.
11-10 RW 0 ICPS
Input Capture Pin Select
00b = icp0;
01b = icp1;
10b = icp2;
11b = icp3.
9-8 RW 0 ICES
Input capture edge select:
00b = positive edge;
01b = negative edge;
10b = positive and negative edge;
11b = reserved.
7 RW 0 ICCLR
Input Capture clear edge selection.
0 = positive edge;
1 = negative edge.