NXP Semiconductors QN902 Series, Руководство пользователя

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NXP Semiconductors
QN902x
User Manual of QN902x
UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
User Manual Rev 1.3
— 05 November 2018
88 of 128
TO
PR
[31
]
TO
PR
[30
]
TO
PR
[29
]
TO
PR
[28
]
TO
PR
[27
]
TO
PR
[26
]
TO
PR
[25
]
TO
PR
[24
]
TO
PR
[23
]
TO
PR
[22
]
TO
PR
[21
]
TO
PR
[20
]
TO
PR
[19
]
TO
PR
[18
]
TO
PR
[17
]
TO
PR
[16
]
TO
PR
[15
]
TO
PR
[14
]
TO
PR
[13
]
TO
PR
[12
]
TO
PR
[11
]
TO
PR
[10
]
TO
PR
[9]
TO
PR
[8]
TO
PR
[7]
TO
PR
[6]
TO
PR
[5]
TO
PR
[4]
TO
PR
[3]
TO
PR
[2]
TO
PR
[1]
TO
PR
[0]
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Type Reset Symbol Description
31-0 RW
FFFFFFF
Fh
TOPR[31-0]
Timer TOP register for Free-running and capture event
mode:
The bit-width of TOPR is same as Timer count; it can be 16
or 32 bits.
For capture count mode, The 16 LSB(32-bit timer) or 8 LSB
(16-bit timer) is used to set the count event.
Table 64 ICER
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
ICE
R
[15
]
ICE
R
[14
]
ICE
R
[13
]
ICE
R
[12
]
ICE
R
[11
]
ICE
R
[10
]
ICE
R
[9]
ICE
R
[8]
ICE
R
[7]
ICE
R
[6]
ICE
R
[5]
ICE
R
[4]
ICE
R
[3]
ICE
R
[2]
ICE
R
[1]
ICE
R
[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
Bit Type Reset Symbol Description
31-16 R 0 RSVD reserved
15-0 R 0 ICER
Input Capture Event Register.
In input capture event mode, it’s the event number occurred
during specified time duration.
The bit width of ICER can be 16 bit or 24 bit.
Table 65 CCR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
C
C
R
[31
]
C
C
R
[30
]
C
C
R
[29
]
C
C
R
[28
]
C
C
R
[27
]
C
C
R
[26
]
CCR
[25
]
C
C
R
[24
]
C
C
R
[23
]
C
C
R
[22
]
C
C
R
[21
]
C
C
R
[20
]
C
C
R
[19
]
C
C
R
[18
]
C
C
R
[17
]
C
C
R
[16
]
C
C
R
[15
]
C
C
R
[14
]
C
C
R
[13
]
C
C
R
[12
]
C
C
R
[11
]
C
C
R
[10
]
C
C
R
[9]
C
C
R
[8]
C
C
R
[7]
C
C
R
[6]
C
C
R
[5]
C
C
R
[4]
C
C
R
[3]
C
C
R
[2]
C
C
R
[1]
C
C
R
[0]
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
Bit Type Reset Symbol Description
31-0 RWH FFFFFFFFh
CCR[31-
0]
Timer input Capture/Compare Register 0:
In free-running m
ode, it’s used as compare register, setting
by software;