NXP Semiconductors MPC5746R, Техническое описание

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1. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.
2. Maximum usable frequency does not take into account external device propagation delay.
18.2.1 DSPI master mode full duplex timing with CMOS and LVDS
pads
The values presented in these sections are target values. A complete performance
characterization of the pads (in all configuration combinations) is required before the
final specifications can be released.
18.2.1.1 DSPI CMOS master mode – classic timing
All output timing is worst case and includes the mismatching of rise and fall times of the
output pads.
NOTE
In Table 40 , all output timing is worst case and includes the
mismatching of rise and fall times of the output pads.
Table 40. DSPI CMOS master classic timing (full duplex and output only) - MTFE = 0, CPHA
= 0 or 1
# Symbol Characteristic Condition Value
1
Unit
Pad drive
2
Load (C
L
) Min Max
1 t
SCK
SCK cycle time SCK drive strength
Very strong
25 pF 33.0 — ns
Strong 50 pF 80.0 —
Medium 50 pF 200.0 —
2 t
CSC
PCS to SCK delay SCK and PCS drive strength
Very strong
25 pF (N
3
x t
SYS
, 4
) - 16 — ns
Strong 50 pF (N
3
x t
SYS
, 4
) - 16 —
Medium 50 pF (N
3
x t
SYS
, 4
) - 16 —
PCS medium and
SCK strong PCS = 50 pF
SCK = 50 pF
(N
3
x t
SYS
, 4
) - 29 —
3 t
ASC
After SCK delay SCK and PCS drive strength
Very strong
PCS = 0 pF
SCK = 50 pF
(M
5
x t
SYS
4
) - 35 — ns
Strong PCS = 0 pF
SCK = 50 pF
(M
5
x t
SYS
, 4
) - 35 —
Medium PCS = 0 pF
SCK = 50 pF
(M
5
x t
SYS
, 4
) - 35 —
PCS medium and
SCK strong PCS = 0 pF (M
5
x t
SYS
, 4
) - 35 —
Table continues on the next page...
AC specifications
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
66 NXP Semiconductors