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UART Modules
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
16-9
16.3.5
UART Command Registers (UCR
n
)
The UART command registers (UCR
n
),
, supply commands to the UART. Only multiple
commands that do not conflict can be specified in a single write to a UCR
n
. For example,
RESET
TRANSMITTER
and
ENABLE
TRANSMITTER
cannot be specified in one write.
describes UCR
n
fields and commands. Examples in
Section 16.5.2, “Transmitter and Receiver
,” show how these commands are used.
7
6
4
3
2
1
0
Field
ENAB
MISC
TC
RC
Reset
0000_0000
R/W
Write only
Address
MBAR + 0x108, 0x148
Figure 16-6. UART Command Registers (UCR
n
)
Table 16-6. UCR
n
Field Descriptions
Bits
Value
Command
Description
7
ENAB
—
Enable autobaud
0 Autobaud disabled.
1 Autobaud enabled. The transmission rate is calculated from the first received
character. If the rate must be recalculated, ENAB must first be cleared and reset.
UISR
n
[ABC] indicates a transmission rate has been calculated and loaded into the
UART divider registers. UDU
n
and UDUL
n
must be initialized to 0x00 before enabling
autobaud.
6–4
MISC Field
(This field selects a single command.)
000
no command
—
001
reset mode register
pointer
Causes the mode register pointer to point to UMR1
n
.
010
reset receiver
Immediately disables the receiver, clears USR
n
[FFULL,RxRDY], and reinitializes the
receiver FIFO pointer. No other registers are altered. Because it places the receiver in
a known state, use this command instead of
RECEIVER
DISABLE
when reconfiguring the
receiver.
011
reset transmitter
Disables the transmitter and clears USR
n
[TxEMP,TxRDY]. No other registers are
altered. Because it places the transmitter in a known state, use this command instead
of
TRANSMITTER
DISABLE
when reconfiguring the transmitter.
100
reset error status
Clears USR
n
[RB,FE,PE,OE]. Also used in block mode to clear all error bits after a data
block is received.
101
reset break– change
interrupt
Clears the delta break bit, UISR
n
[DB].
110
start break
Forces TxD low. If the transmitter is empty, the break may be delayed up to one bit time.
If the transmitter is active, the break starts when character transmission completes. The
break is delayed until any character in the transmitter shift register is sent. Any character
in the transmitter holding register is sent after the break. The transmitter must be
enabled for the command to be accepted. This command ignores the state of CTS.
111
stop break
Causes TxD to go high (mark) within two bit times. Any characters in the transmitter
buffer are sent.
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