NXP Semiconductors MCF5272 ColdFire, Руководство пользователя

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SDRAM Controller
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
9-14 Freescale Semiconductor
Selecting a system clock frequency low enough that the SDCLK-to-CLK delay is long compared to the
SDRAM read access time reduces effective CAS latency by 1 cycle.
Figure 9-8. Timing Refinement with Effective CAS Latency
NOTE
When reduced effective CAS latency is used, the SDRAM is still
programmed with true CAS latency. The SDRAM controller state machine
must be reprogrammed for the reduced CAS latency. SDRAM initialization
software programs the CAS latency of 2 and transfers it into the SDRAM
mode register. After SDRAM initialization is confirmed, initialization
software should change SDTR[CLT] to CAS latency 1 but should not
reinitialize the SDRAM. The SDRAM controller state machine now runs
with CAS latency 1 and SDRAMs run with CAS latency 2, which increases
bandwidth on the SDRAM bank and improves performance.
9.10 SDRAM Interface
Setting CSBR n [EBI] to 0b01 enables chip select CS7 for use with one physical bank of SDRAM. In this
case, CS7 becomes SDCS. The SDRAM memory array may have a 32- or 16-bit data bus width; an 8-bit
width is not supported. An array may consist of SDRAM devices with 8, 16, or 32 bits data bus width.
Each SDRAM device can have from 16–256 Mbits.
The interface to the SDRAM devices is glueless. The following control signals are dedicated to SDRAM:
SDCS, SDWE, A10_PRECHG, SDCLK, SDCLKE, RAS0, CAS0, and SDBA[1:0].
If SDRAM EBI mode is used, CSOR7[WAITST] should be programmed for 0x1F to ensure that the
internal bus cycle termination signal is sourced from the SDRAM controller and not the chip select
module.
Shifted delay of SDCLK
Delay SDCLK to CLK
SDRAM read access time
T
SDCLK_to_CLK
- T
acc
> 0 => effective CAS latency reduced by 1
CASL = 1
SDCLK
Data
Internal CLK