NXP Semiconductors MCF5272 ColdFire, Руководство пользователя

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Local Memory
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor 4-11
For all cases of a line-sized fetch, the critical longword defined by miss address bits 3–2 is accessed first
followed by the remaining three longwords that are accessed by incrementing the longword address in
0-modulo-16 increments, as shown below:
if miss address[3:2] = 00
fetch sequence = {0x0, 0x4, 0x8, 0xC}
if miss address[3:2] = 01
fetch sequence = {0x4, 0x8, 0xC, 0x0}
if miss address[3:2] = 10
fetch sequence = {0x8, 0xC, 0x0, 0x4}
if miss address[3:2] = 11
fetch sequence = {0xC, 0x0, 0x4, 0x0x8}
When an external fetch is initiated and data is loaded into the line-fill buffer, the instruction cache
maintains a special most-recently-used indicator that tracks the contents of the fill buffer versus its
corresponding cache location. At the time of the miss, the hardware indicator is set, marking the fill buffer
as most recently used. If a subsequent access occurs to the cache location defined by bits 9–4 of the fill
buffer address, the data in the cache memory array is now most-recently used, so the hardware indicator
is cleared. In all cases, the indicator defines whether the contents of the line-fill buffer or the cache memory
data array are most recently used. If the entire line is present at the time of the next cache miss, the line-fill
buffer contents are written into the cache memory array and the fill buffer data is still most recently used
compared to the cache memory array.
The fill buffer can also be used as temporary storage for line-sized bursts of non-cacheable references
under control of CACR[CEIB]. With this bit set, a noncacheable instruction fetch is processed as defined
by
Table 4-6 . For this condition, the fill buffer is loaded and subsequent references can hit in the buffer,
but the data is never loaded into the cache memory array.
Table 4-6 shows the relationship between CENB, CEIB, and the type of instruction fetch.
Table 4-6. Instruction Cache Operation as Defined by CACR[CENB,CEIB]
CACR[CENB,CEIB] Type of Fetch Description
00 N/A Instruction cache and line-fill buffer are disabled; fetches are word or longword in
size.
01 N/A Instruction cache is disabled but because the line-fill buffer is enabled, CACR[CLNF]
defines fetch size and instructions can be bursted into the line-fill buffer.
1X Cacheable Cache is enabled; CACR[CLNF] defines fetch size and line-fill buffer contents can be
written into the cache memory array.
10 Noncacheable Cache is enabled but the linefill buffer is disabled; fetches are either word or
longword and are not loaded into the line-fill buffer.
11 Noncacheable Cache and line buffer are enabled; CACR[CLNF] defines fetch size; fetches are
loaded into the line-fill buffer but never into the cache memory array.