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NXP Semiconductors
UM11192
User Manual for LPCXpresso54S018M Development Board
UM11192
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
User manual
Rev. 1.0
— 13th February 2019
6 of 34
Fig 3.
Jumper locations
Table 1
lists the function of each jumper.
Table 1.
Jumpers
Circuit ref
Description
Section
JP1
Target processor selection for the on-board Debug Probe.
Jumper open (default) the LPC54S018J4M Target SWD interface
enabled. Normal operating mode where the Target SWD is
connected to either the on-board Link2 Debug Probe or an external
Debug Probe.
Jumper shunted, the LPC54S018J4M Target SWD interface is
disabled. Use this setting only when the on-board Link2 Debug
Probe is used to debug an off-board target MCU.
3
,
4
JP2
Buffer Power Selection
For On-board Target place in position 1-2 (default)
For Off-board Target place in position 2-3
3
,
4
JP3
This header (not installed by default) provides a convenient
connection point to provide external ADC positive and negative
voltages. To inject these voltages at this header SJ22 (for VREFN)
and/or SJ23 (for VREFP) need to be moved from the default 1-2
position to the 2-3 position.
See
Schematic