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NXP Semiconductors
UM11192
User Manual for LPCXpresso54S018M Development Board
UM11192
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
User manual
Rev. 1.0
— 13th February 2019
18 of 34
Fig 5.
Identifying the VCOM port
If the J-Link firmware image has been programmed into the Debug Probe and DFU boot
mode is not being used, then a VCOM device called Jlink CDC UART port will appear
instead of the LPC-LinkII UCom port.
5.4 Configuring the LPCXpresso54S018M to debug an external target
The LPCXpresso54S018M
board’s Link2 Debug Probe may be used to debug an off-
board target MCU. The on-board Link2 Debug Probe is capable of debugging target
MCU’s with a VDDIO range of 1.6V to 3.6V. To keep the on-board target
LPC54S018J4M MCU from interfering with the SWD interface, JP1 must be fitted. The
Link2 Debug Probe SWD should be connected by a ribbon cable between the P1
connector to the off-board target MCU SWD interface. Power the LPCXpresso54S018M
board from the Link USB connector J8, and fit jumper JP2 across pins 2 - 3 (External
Target).
6. Troubleshooting debug sessions
In some cases, the ability to make a debug connection can be lost due to the LPC54xxx
target running code that does not allow the host debugger system to gain control of it.
Some reasons for this can be:
•
Application code causing a hard fault
•
Application code disabling the SWD debug port pins
•
The boot image has an invalid header
In many cases, the board can be put back in a state where the debugger can gain control
by using the ISP buttons and pressing and releasing the reset button (for example,
holding down ISP0 to force the device into the serial ISP boot mode). If problems persist
with ISP mode entry being required, try mass erasing the flash; this can be done using
the MCUXpresso IDE device programming utility.
LPC54S018JxM devices do not have any pull-ups enabled at reset, and in cases where
an application is using the SDRAM this could cause the EMC_D2 through EMC_D4
signals to be driven by that device (since the P1_12 port of the target could be floating).
Since these signals are shared with the ISP0-2 pins, an undesired ISP boot mode could