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Table 21-2. Flash Option Register (FTFE_FOPT) definition
(continued)
Bit
Num
Field
Value
Definition
0
NMI interrupts are always blocked. The associated pin continues to default to
NMI_b pin controls with internal pullup enabled. When NMI_b pin function is
disabled, it cannot be used as a source for low-power mode wake-up.
If the NMI function is not required, either for an interrupt or wake up source, it is
recommended that the NMI function be disabled by clearing NMI_DIS.
1
NMI_b pin/interrupts reset default to enabled.
1
BOOTPIN_OPT
External pin selects boot options
0
Force Boot from ROM with update if BOOTCFG0 asserted, where BOOTCFG0 is
the boot config function which is muxed with NMI pin. The RESET pin should be
enabled when this option is selected.
1
Boot source configured by FOPT[7] (BOOTSRC_SEL) bitfield
0
LPBOOT
Controls the reset value of clock divider of IRC48M to feed the core clock. Larger divide
value selections produce lower average power consumption during POR and reset
sequencing and after reset exit. The recovery times are also extended .
0
Low-power boot: Core and system clock divider (DIVCORE) is 0x1 (divide by 2).
1
Normal boot: Core and system clock divider (DIVCORE) is 0x0 (divide by 1).
This device supports cold booting from either internal flash or Boot ROM.
When the device boots from internal flash, the reset vectors are located at address 0x0
(initial SP_main) and 0x4 (initial PC).
When the device boots from ROM, the chip will re-map the reset vectors to ROM start
address at 0x1C00_0000 where SP_main is offset 0x0 and PC is offset 0x4. When Boot
ROM completes, software can clear RCM mode register (RCM_MR) to disable
remapping of vector fetches. Boot source can change between reset, but is always known
before core reset negation. NMI input is disabled to platform when booting from ROM.
See
for more detail options.
The device also supports relocating the exception vector table to RAM. This is
implemented through a programmable Vector Table Offset Register (VTOR) in SCB
module.
The boot options can be overridden by using RCM_FM[2:1] and RCM_MR[2:1] which
can be written by software. The boot source remains set until the next System Reset or
software can write logic one to clear one or both of the mode bits.
Boot
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
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NXP Semiconductors
Содержание Kinetis KE1xZ256
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Страница 56: ...SysTick Clock Configuration Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 56 NXP Semiconductors...
Страница 62: ...Interrupt channel assignments Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 62 NXP Semiconductors...
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Страница 368: ...Module clocks Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 368 NXP Semiconductors...
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