NXP Semiconductors freescale KV4 Series, Справочное руководство

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Table 23-294. Hardware service request process
Cycle Description
With internal peripheral
bus read and internal
SRAM write
With SRAM read and
internal peripheral bus
write
1 eDMA peripheral request is asserted.
2 The eDMA peripheral request is registered locally in the
eDMA module and qualified. TCD
n _CSR[START] bit initiated
requests start at this point with the registering of the user
write to TCD
n word 7.
3 Channel arbitration begins.
4 Channel arbitration completes. The transfer control descriptor
local memory read is initiated.
5–6 The first two parts of the activated channel's TCD is read from
the local memory. The memory width to the eDMA engine is
64 bits, so the entire descriptor can be accessed in four
cycles
7 The first system bus read cycle is initiated, as the third part of
the channel's TCD is read from the local memory. Depending
on the state of the crossbar switch, arbitration at the system
bus may insert an additional cycle of delay here.
8–11 8–12 The last part of the TCD is read in. This cycle represents the
first data phase for the read, and the address phase for the
destination write.
12 13 This cycle represents the data phase of the last destination
write.
13 14 The eDMA engine completes the execution of the inner minor
loop and prepares to write back the required TCD
n fields into
the local memory. The TCD n word 7 is read and checked for
channel linking or scatter/gather requests.
14 15 The appropriate fields in the first part of the TCD n are written
back into the local memory.
15 16 The fields in the second part of the TCD n are written back into
the local memory. This cycle coincides with the next channel
arbitration cycle start.
16 17 The next channel to be activated performs the read of the first
part of its TCD from the local memory. This is equivalent to
Cycle 4 for the first channel's service request.
Assuming zero wait states on the system bus, DMA requests can be processed every 9
cycles. Assuming an average of the access times associated with internal peripheral bus-
to-SRAM (4 cycles) and SRAM-to-internal peripheral bus (5 cycles), DMA requests can
be processed every 11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle 4 to Cycle x
+5. The resulting peak request rate, as a function of the system frequency, is shown in the
following table.
Chapter 23 Direct Memory Access Controller (eDMA)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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