MC56F8367EVM User Manual, Rev. 2
2-6
Freescale Semiconductor
Preliminary
2.2.2 SRAM Bank 1
SRAM bank 1, which is controlled by CS1 and CS2, uses a 128K x 16-bit Fast Static RAM (GSI
GS72116, labeled U3) for external memory expansion; see the FSRAM schematic diagram in
. Using CS1 and CS4, this memory bank can be configured as byte (8-bit) or word
(16-bit) accessable Program memory, Data memory, or both. Additionally, CS1 and CS4 can be
configured to assign this memory’s size and starting address to any modulo address space.
This memory bank will operate with zero wait state access while the 56F8367 is running at
60MHz and can be disabled by removing the jumpers at JG8.
MC56F8367
GS72116
A0 - A16
D0 - D15
RD
WR
A0 - A16
DQ0 - DQ15
OE
WE
CE
JG8
Jumper Pin 1-2:
Enable SRAM Low Byte
DS / CS1
PD2 / CS4
LB
HB
Jumper Pin 3-4:
Enable SRAM High Byte
1
3
2
4
Figure 2-2. Schematic Diagram of the External CS1 / CS4 Memory Interface
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