Program and Data Memory
Technical Summary, Rev. 2
Freescale Semiconductor
2-5
Preliminary
2.2.1 SRAM Bank 0
SRAM bank 0, which is controlled by CS0, uses a 128K x 16-bit Fast Static RAM (GSI
GS72116, labeled U2) for external memory expansion; see the FSRAM schematic diagram in
. CS0 can be configured to use this memory bank as 16 bits of Program memory, Data
memory, or both. Additionally, CS0 can be configured to assign this memory’s size and starting
address to any modulo address space.
This memory bank will operate with zero wait state access while the 56F8367 is running at
60MHz and can be disabled by removing the jumper at JG7.
MC56F8367
GS72116
A0 - A16
D0 - D15
RD
WR
A0 - A16
DQ0 - DQ15
OE
WE
CE
1
2
JG7
+3.3V
Jumper Pin 1-2:
Enable SRAM
PS / CS0
Jumper Removed:
Disable SRAM
Figure 2-1. Schematic Diagram of the External CS0 Memory Interface
Содержание 56F8367
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