NVIDIA Jetson TX2/TX2i OEM Product Design Guide
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
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Pin #
Module Pin
Name
Tegra Signal
Usage/Description
Usage on the
Carrier Board
Direction
Pin Type
C46
PEX2_CLKREQ#
PEX_L1_CLKREQ_N
PCIE 2 Clock Request (PCIe IF #1)
Bidir
Open Drain 3.3V, Pull-
up on the module
D49 PEX2_RST#
PEX_L1_RST_N
PCIe 2 Reset (PCIe IF #1)
Output
F43
USB
PEX_RX0P
USB SS 0 (USB 3.0 Port #0 muxed w/PCIe #2
Lane 0)
USB 3.0 Type A
Input
USB SS PHY, AC-
Coupled (off the
module)
F44
USB_SS0_RX
–
PEX_RX0N
USB SS 0 Receive
–
(USB 3.0 Port #0 muxed w/PCIe #2
Lane 0)
Input
C43
USB
PEX_TX0P
USB SS 0 T (USB 3.0 Port #0 muxed w/PCIe #2
Lane 0)
Output
USB SS PHY, AC-
Coupled on carrier
board
C44
USB_SS0_TX
–
PEX_TX0N
USB SS 0 Transmit
–
(USB 3.0 Port #0 muxed w/PCIe #2
Lane 0)
Output
G45
PEX_RX5P
SATA
SATA Connector
Input
SATA PHY, AC-Coupled
on carrier board
G46 SATA_RX
–
PEX_RX5N
SATA Receive
–
Input
D45
PEX_TX5P
SATA T
Output
D46 SATA_TX
–
PEX_TX5N
SATA Transmit
–
Output
D47 SATA_DEV_SLP
PEX_L2_CLKREQ_N
SATA Device Sleep or PEX1_CLKREQ# (PCIe IF #2)
depending on Mux setting
Input
Open Drain 3.3V, Pull-
up on the module
The table below show several w ays to bring out as many of the USB 3.0 or PCIe interf aces as possible to meet different design
requirements for a platform built for Jetson TX2/TX2i.
Note:
Check the Jetson TX1 and Jetson TX2 Comparison and Migration Application Note which
provides the differences in USB 3.0, PCIe & SATA lane mapping between Jetson TX1 & Jetson
TX2/TX2i and provides a table of configurations supported by all three modules.
Table 15. USB 3.0, PCIe & SATA Lane Mapping Configurations
Module Pin Names
PEX1
PEX_RFU
PEX2
USB_SS1
PEX0
USB_SS0
(see note 1)
SATA
Tegra Lanes
Lane 0
Lane 1
Lane 3
Lane 2
Lane 4
Lane 5
Avail. Outputs from the
module
Configs
USB 3.0
PCIe
SATA
1
0
1x1 + 1x4
1
PCIe#2_0
PCIe#0_3
PCIe#0_2
PCIe#0_1
PCIe#0_0
SATA
2 (CB
Default)
1
1x4
1
PCIe#0_3
PCIe#0_2
PCIe#0_1
PCIe#0_0
USB_SS#0
SATA
3
2
3x1
1
PCIe#2_0
USB_SS#1
PCIe#1_0
USB_SS#2
PCIe#0_0
SATA
4
3
2x1
1
USB_SS#1
PCIe#1_0
USB_SS#2
PCIe#0_0
USB_SS#0
SATA
5
1
2x1 + 1x2
1
PCIe#2_0
USB_SS#1
PCIe#1_0
PCIe#0_1
PCIe#0_0
SATA
6
2
1x1 + 1x2
1
USB_SS#1
PCIe#1_0
PCIe#0_1
PCIe#0_0
USB_SS#0
SATA
Default Usage on CB (carrier board)
Unused
X4 PCIe Connector
USB 3 Type A
SATA
Note:
1.
PCIe interface #2 can be brought to the PEX1 pins, or USB 3.0 port #1 to the USB_SS0 pins on Jetson TX2/TX2i depending
on the setting of a multiplexor on the module. The selection is controlled by QSPI_IO2 configured as a GPIO.
2.
Jetson TX2/TX2i has been designed to enable use cases listed in the table above. However, released Software may not
support all configurations, nor has every configura tion been validated.
o
Configuration #1 & 2 represent the supported and validated Jetson TX2/TX2i Developer Kit configurations. These
configurations are supported by the released Software, and the PCIe, USB 3.0, and SATA interfaces have been
verified on the carrier board.
3.
The cell colors highlight the different PCIe interfaces and USB 3.0 ports. Light and Medium green are used for PCIe
controllers #0 and #1. Four shades of blue are used for USB 3.0 controllers #[0:3]. SATA is highlighted in orange.
4.
Any x4 configuration can be used as a single x2 using only lanes 0 & 1 or a single x1 using only lane 0. Any x2
configuration can be used as a single x1 using only lane 0.
5.
In order to ease routing, the order of lanes for PCIe #0 can either be as shown above, or the reverse (I.e., PCIE#0_3 on
lane 4, PCIE#0_2 on lane 3, etc.).