Nvidia JETSON TX2, Руководство пользователя

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NVIDIA Jetson TX2/TX2i OEM Product Design Guide
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618 99
Pin # Module Pin Name Tegra Signal Usage/Description
Usage on the Carrier
Board
Direction Pin Type
D40 PEX_RFU_TX – PEX_TX1N
PCIe RFU Transmit – (PCIe IF #0 Lane 3
or USB 3.0 Port #1)
Output
D41 GND − GND GND − GND
D42 USB PEX_TX2P
USB SS 1 T (USB 3.0 Port #2 or
PCIe IF #0 Lane 1)
PCIe x4 Connector
Output
USB SS PHY, AC-Coupled on
carrier board
D43 USB_SS1_TX – PEX_TX2N
USB SS 1 Transmit – (USB 3.0 Port #2 or
PCIe #0 Lane 1)
Output
D44 GND − GND GND − GND
D45 PEX_TX5P SATA T
SATA Connector
Output
SATA PHY, AC-Coupled on
carrier board
D46 SATA_TX – PEX_TX5N SATA Transmit – Output
D47 SATA_DEV_SLP PEX_L2_CLKREQ_N
SATA Device Sleep or PEX1_CLKREQ#
(PCIe IF #2) depending on Mux setting
Input
Open Drain 3.3V, Pull-up on
the module
D48 PEX_WAKE# PEX_WAKE_N PCIe Wake PCIe x4 conn & M.2 Input
Open Drain 3.3V, Pull-up on
the module
D49 PEX2_RST# PEX_L1_RST_N PCIe 2 Reset (PCIe IF #1) Unassigned Output
D50 RSVD − Not used − − −
E1 FORCE_RECOV# GPIO_SW1 Force Recovery strap pin System Input CMOS – 1.8V
E2 SLEEP# GPIO_SW2
Sleep Request to the module from the
carrier board. An internal Tegra pull-up
is present on the signal.
Sleep (VOL DOWN)
button
Input CMOS – 1.8V (see note 3)
E3 SPI0_CLK GPIO_SEN1 SPI 0 Clock
Display Connector
Bidir CMOS – 1.8V
E4 SPI0_MISO GPIO_SEN2 SPI 0 Master In / Slave Out Bidir CMOS – 1.8V
E5 I2S3_SDIN DAP4_DIN I2S Audio Port 3 Data In
Camera Connector
Input CMOS – 1.8V
E6 I2S3_CLK DAP4_SCLK I2S Audio Port 3 Clock Bidir CMOS – 1.8V
E7 CAM2_MCLK GPIO_CAM2 Camera 2 Master Clock Output CMOS – 1.8V
E8 CAM_VSYNC QSPI_IO1 Camera Vertical Sync Output CMOS – 1.8V
E9 UART1_RTS# UART3_RTS UART 1 Request to Send
Serial Port Header
Output CMOS – 1.8V
E10 UART1_CTS# UART3_CTS UART 1 Clear to Send Input CMOS – 1.8V
E11 RSVD − Not used − − −
E12 RSVD − Not used − − −
E13 RSVD − Not used − − −
E14 SPI1_CS0# GPIO_CAM7 SPI 1 Chip Select 0 Expansion Header Bidir CMOS – 1.8V
E15 I2C_GP0_CLK GPIO_SEN8 General I2C 0 Clock I2C (General) Bidir Open Drain – 1.8V
E16 AO_DMIC_IN_CLK CAN_GPIO1 Digital Mic Input Clock Expansion Header Output CMOS – 1.8V
E17 RSVD − Not used − − −
E18 CAN0_ERR CAN_GPIO5 CAN 0 Error
GPIO Expansion
Header
Input CMOS 3.3V
E19 GND − GND GND − GND
E20 CSI5_D1 – CSI_F_D1_N Camera, CSI 5 Data 1 –
Camera Connector
Input
MIPI D-PHY
E21 CSI_F_D1_P Camera, CSI 5 Data 1+ Input
E22 GND − GND GND − GND
E23 CSI3_D1 – CSI_D_D1_N Camera, CSI 3 Data 1 –
Camera Connector
Input
MIPI D-PHY
E24 CSI_D_D1_P Camera, CSI 3 Data 1+ Input
E25 GND − GND GND − GND
E26 CSI1_D1 – CSI_B_D1_N Camera, CSI 1 Data 1 –
Camera Connector
Input
MIPI D-PHY
E27 CSI_B_D1_P Camera, CSI 1 Data 1+ Input
E28 GND − GND GND − GND
E29 DSI_D_D1_P Display, DSI 3 Data 1+
Display Connector
Output
MIPI D-PHY
E30 DSI3_D1 – DSI_D_D1_N Display, DSI 3 Data 1 – Output
E31 GND − GND GND − GND
E32 DSI_B_D1_P Display, DSI 1 Data 1+
Display Connector
Output
MIPI D-PHY
E33 DSI1_D1 – DSI_B_D1_N Display, DSI 1 Data 1 – Output
E34 GND − GND GND − GND
E35 DP1_TX3 – HDMI_DP1_TXDN3 DisplayPort 1 Lane 3 – or HDMI Clk Lane –
HDMI Type A Conn.
Output
AC-Coupled on carrier
board
E36 HDMI_DP1_TXDP3 DisplayPort 1 Lane 3+ or HDMI Clk Lane+ Output
E37 GND − GND GND − GND
E38 DP1_TX0 – HDMI_DP1_TXDN2 DisplayPort 1 Lane 0 – or HDMI Lane 2 –
HDMI Type A Conn.
Output
AC-Coupled on carrier
board
E39 HDMI_DP1_TXDP2 DisplayPort 1 Lane 0+ or HDMI Lane 2+ Output
E40 GND − GND GND − GND
E41 PEX_TX0P
PCIe 1 T (PCIe #2 Lane 0 muxed
w/USB 3.0 Port #0)
USB 3.0 Type A
(Default) or M.2 Key E
Output
PCIe PHY, AC-Coupled on
carrier board
E42 PEX1_TX – PEX_TX0N
PCIe 1 Transmit – (PCIe #2 Lane 0 muxed
w/USB 3.0 Port #0)
Output
E43 GND − GND GND − GND