Nuvoton ARM Cortex NuMicro M451 Series, Техническое справочное руководство

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M451
May. 4, 2018 Page 783 of 1006 Rev.2.08
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S Status Register (SPI_I2SSTS)
Register Offset R/W Description Reset Value
SPI_I2SSTS 0x68 R/W I
2
S Status Register 0x0005_0100
Note: Not supported in SPI mode.
31 30 29 28 27 26 25 24
Reserved TXCNT Reserved RXCNT
23 22 21 20 19 18 17 16
TXRXRST Reserved LZCIF RZCIF TXUFIF TXTHIF TXFULL TXEMPTY
15 14 13 12 11 10 9 8
I2SENSTS Reserved RXTOIF RXOVIF RXTHIF RXFULL RXEMPTY
7 6 5 4 3 2 1 0
Reserved RIGHT Reserved
Bits Description
[31] Reserved Reserved.
[30:28] TXCNT
Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
[27] Reserved Reserved.
[26:24] RXCNT
Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
[23] TXRXRST
TX or RX Reset Status (Read Only)
0 = The reset function of TXRST or RXRST is done.
1 = Doing the reset function of TXRST or RXRST.
Note: Both the reset operations of TXRST and RXRST need 3 system clock 3
peripheral clock cycles. User can check the status of this bit to monitor the reset function is
doing or done.
[22] Reserved Reserved.
[21] LZCIF
Left Channel Zero Cross Interrupt Flag
0 = No zero cross event occurred on left channel.
1 = Zero cross event occurred on left channel.
[20] RZCIF
Right Channel Zero Cross Interrupt Flag
0 = No zero cross event occurred on right channel.
1 = Zero cross event occurred on right channel.
[19] TXUFIF
Transmit FIFO Underflow Interrupt Flag
When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer,
if there is more bus clock input, this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
[18] TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
0 = The valid data count within the transmit FIFO buffer is larger than the setting value of
TXTH.
1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting