Nuvoton ARM Cortex NuMicro M451 Series, Техническое справочное руководство

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M451
May. 4, 2018 Page 350 of 1006 Rev.2.08
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Insert Idle Cycle
When EBI accessing continuously, there may occur bus conflict if the device access time is much
slow with system operating. EBI controller supply additional idle cycle to solve this problem.
During idle cycle, all control signals of EBI are inactive. Figure 6.5-6 shows idle cycle.
EBI_nCS
EBI_AD[15:0]
EBI_MCLK
EBI_nRD
tACC tASU tAHD
EBI_nWR
EBI_AD[15:0]
EBI_ALE
tALE tLHD tA2D
Address
output[15:0]
WData output[15:0]
RData
input
Idle cycle
XX
tASU tALE
Address
output[15:0]
Address
output[15:0]
Address
output[15:0]
EBI_ADR[18:16] Address output[18:16]
EBI_ADR[18:16] Address output[18:16]
Note: The EBI_MCLK is HCLK/2, MCLKDIV (EBI_CTLx[10:8]) = 1
Figure 6.5-6 Timing Control Waveform for Insert Idle Cycle
There are two conditions that EBI can insert idle cycle by timing control:
1. After write access
2. After read access and before next read access (R2R idle cycle)
By setting W2X (EBI_TCTLx[15:12]), and R2R (EBI_TCTLx[27:24]), the time of idle cycle can be
specified from 0~15 EBI_MCLK.
Write Buffer
When user write a data to external device through EBI bus, the EBI controller will start processing
the write action immediately and the CPU is held until current EBI write action finish. User can
enable write buffer function to improve CPU and EBI access performance. When EBI write buffer
function is enabled, the CPU can continuous execute other instruction during EBI controller
process the write action to external device. There is one exception condition for this case, if CPU
executes another data access through EBI bus when EBI process write action, the CPU will be
held.