Nuvoton ARM Cortex NuMicro M451 Series, Техническое справочное руководство

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M451
May. 4, 2018 Page 752 of 1006 Rev.2.08
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The data stored in the transmit FIFO buffer will be read and sent out by the transmission control
logic. If the transmit FIFO buffer is full, the TXFULL (SPI_STATUS[17]) will be set to 1. When the
SPI transmission logic unit draws out the last datum of the transmit FIFO buffer, so that the
transmit FIFO buffer is empty, the TXEMPTY (SPI_STATUS[16]) will be set to 1. Notice that the
TXEMPTY (SPI_STATUS[16]) flag is set to 1 while the last transaction is still in progress. In
Master mode, the BUSY (SPI_STATUS[0]) is set to 1 when the FIFO buffer is written any data or
there is any transaction on the SPI bus. (e.g. the slave selection signal is active and the SPI
controller is receiving data in slave mode). It will set to 0 when the transmit FIFO is empty and the
current transaction has done. Thus, the status of BUSY (SPI_STATUS[0]) should be checked by
software to make sure whether the SPI is in idle or not.
The receive control logic will store the SPI input data into the receive FIFO buffer. There are FIFO
related status bits, like RXEMPTY (SPI_STATUS[8]) and RXFULL (SPI_STATUS[9]), to indicate
the current status of RX FIFO buffer.
The transmitting and receiving threshold can be configured by setting TXTH
(SPI_FIFOCTL[30:28]) and RXTH (SPI_FIFOCTL[26:24]). When the count of valid data stored in
transmit FIFO buffer is less than or equal to TXTH (SPI_FIFOCTL[30:28]) setting, TXTHIF
(SPI_STATUS[18]) will be set to 1. When the count of valid data stored in receive FIFO buffer is
larger than RXTH (SPI_FIFOCTL[26:24]) setting, RXTHIF (SPI_STATUS[10]) will be set to 1.
Comparator
Valid Data Count in
Transmit FIFO Buffer
TXTHIF = 1 when A <= B
TXTHIF = 0 when A > B
TXTH
Comparator
Valid Data Count in
Receive FIFO Buffer
RXTH
A
B
A
B
RXTHIF = 1 when A > B
RXTHIF = 0 when A <= B
Figure 6.16-17 FIFO Threshold Comparator
In Master mode, the first datum is written to the SPI_TX register, the TXEMPTY flag
(SPI_STATUS[16]) will be cleared to 0. The transmission will start after 1 APB clock cycle and 6
peripheral clock cycles. User can write the next data into SPI_TX register immediately. The SPI
controller will insert a suspend interval between two successive transactions. The period of
suspend interval is decided by the setting of SUSPITV (SPI_CTL[7:4]). If the SUSPITV
(SPI_CTL[7:4]) equals 0, SPI controller can perform continuous transfer. User can write data into
SPI_TX register as long as the TXFULL (SPI_STATUS[17]) is 0.
In the Example 1 of the Figure 6.16-18, it indicates the updated condition of TXEMPTY
(SPI_STATUS[16]) and the relationship among the FIFO buffer, shift register and the skew buffer.
The TXEMPTY (SPI_STATUS[16]) is set to 0 when the Data 0 is written into the FIFO buffer. The
Data 0 will be loaded into the shift register by core logical and the TXEMPTY (SPI_STATUS[16])
will be to 1. The Data 0 in shift register will be shifted into skew buffer by bit for transmission until
the transfer is done.
In the Example 2, it indicates the updated condition of TXFULL (SPI_STATUS[17]) when there
are 8 data in the FIFO buffer and the next data of Data 9 does not be written into the FIFO buffer
when the TXFULL = 1.