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DA70131-1/3E
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5-1-3. Input change interrupt
When the status of an input port changes, the center device can output an interrupt request to a CPU.
A bit corresponding to any input port number whose status changed can be set to 1 in the interrupt setting
register. And, if the input port data changed while receiving cyclic communication data, the center device will
output an interrupt request to a CPU, and it will change the bit in the input change interrupt flag register which
corresponds to the input port number to 1.
Then, the CPU checks the "input change interrupt" status (IOPC = 1) when an interrupt occurs, and reads the
input change interrupt flag to identify which input port changed.
By writing back the flag data just read, the interrupt can be reset.
- In the case of an I/O device (G9002A)
If the input port data changed while receiving I/O data, an input change interrupt will occur.
- In the case of data device (G9103A, G9004A).
If bit 0 on input port 0 changes from 0 to 1, an input change interrupt will occur. For ports other than input port
0, if the input port data changes an input change interrupt will occur the same way as the case of I/O device
(G9002A).
The PCL device (G9103A) handles the status register (16 bits) as input ports 0 and 1, and the general-purpose
I/O terminal status register as input port 2 data using cyclic communication.
The status register consists of bits to stop operation, to indicate an error has happened, and to indicate an event
has occurred.
Using the input change interrupt function, the center device can output an interrupt request by changing the
status of the PCL device (G9103A).
5-1-4. Break function (when RENV0(8) = 0)
Local devices have BRK terminals. By applying a HIGH to the terminal for a certain length of time (to create a
break signal), the local device will enter the break-waiting status.
Also, the center device periodically sends a "break frame sending request" to the local devices (every 16384
cycles in cyclic communication, or approximately every 250 msec. at 20 Mbps).
The local devices in break-waiting status send break frames when they receive a "break frame send request."
(More than one device may send a break at once.)
The center device recognizes the break frame and outputs an interrupt request to a CPU. It also sets the "BRK"
bit (bit 1) in the status register to "1."
This function is used to increase devices and restore the devices that were excluded from the system due to an
error and so on.
The CPU detects an interrupt caused by a break and can then issue a system communication command. This
allows it to refresh all the devices in polling operation, or to refresh the "device information" for devices that are
currently stopped.
5-1-5. Control of communication errors
1) Cyclic communication errors
When a cyclic communication error occurs, the center device does not retry the communication. However, if
it fails to communicate three times in a row (three consecutive cycles), a cyclic communication error occurs,
and the center device sets the cyclic communication error flag bit that corresponds to the I/O device number
to 1. Also, when bit 3 in the RENV0 register is 0, the center device outputs an interrupt request to the CPU.
The CPU checks the "existence of a cyclic communication error interrupt" (EIOE = 1) in the status register when
an interrupt occurs and then reads the cyclic communication error flags to see which I/O device (G9002A) has an
error.
By writing back the flag data just read, the interrupt is reset.
If needed, the device with an error can be excluded from further cyclic communication by software processing in
the CPU.
Содержание Motionnet G9001A
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