DA70131-1/3E
I-6
4. Hardware description
4-1. A list of terminals (QFP-64)
No.
Name
I/O
Logic
Description
Option
1
IF0
I
-
CPU-I/F mode setting bit 0
U
5V
2
IF1
I
-
CPU-I/F mode setting bit 1
U
5V
3
____
CS
I
Negative
Select chip
5V
S
4
____
WR (R/W)
I
Negative
Write
5V
S
5
____
RD
I
Negative
Read
5V
S
6
A0(LS)
I
Positive
Address bus bit 0 (LSB)
5V
S
7
A1
I
Positive
Address bus bit 1
5V
S
8
A2
I
Positive
Address bus bit 2
5V
S
9
A3
I
Positive
Address bus bit 3
5V
S
11
A4
I
Positive
Address bus bit 4
5V
S
12
A5
I
Positive
Address bus bit 5
5V
S
13
A6
I
Positive
Address bus bit 6
5V
S
14
A7
I
Positive
Address bus bit 7
5V
S
15
A8
I
Positive
Address bus bit 8
5V
S
17
D0
B
Positive
Data bus bit 0 (LSB)
5V
S
18
D1
B
Positive
Data bus bit 1
5V
S
19
D2
B
Positive
Data bus bit 2
5V
S
20
D3
B
Positive
Data bus bit 3
5V
S
22
D4
B
Positive
Data bus bit 4
5V
S
23
D5
B
Positive
Data bus bit 5
5V
S
24
D6
B
Positive
Data bus bit 6
5V
S
25
D7
B
Positive
Data bus bit 7
5V
S
27
D8
B
Positive
Data bus bit 8
5V
S
28
D9
B
Positive
Data bus bit 9
5V
S
29
D10
B
Positive
Data bus bit 10
5V
S
30
D11
B
Positive
Data bus bit 11
5V
S
32
D12
B
Positive
Data bus bit 12
5V
S
33
D13
B
Positive
Data bus bit 13
5V
S
34
D14
B
Positive
Data bus bit 14
5V
S
35
D15
B
Positive
Data bus bit 15
5V
S
37
_____
INT
O
Negative
Interrupt request
5V
38
_____
WRQ
(ACK)
O
Negative
Wait request (
_______
DTACK signal in 68000 CPU)
5V
39
_____
IFB
O
Negative
CPU I/F is busy
5V
40
______
MCRY
O
Negative
By detecting a communication line signal, this signal
becomes L for a rated interval.
5V
41
______
MERR
O
Negative
When received an error frame and no response, this
signal becomes L level for a rated interval.
5V
43
______
MERF
O
Negative
When receiving an error response frame, this signal
becomes L level for a rated interval.
5V
44
MSYN
O
-
The level reverses at each cyclic cycle.
5V
45
______
SOEL
O
Negative
Enable serial output
5V
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