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DDS9m Manual

3.11  High Speed Interface Installation. The
DDS9m can also be controlled by using connections
to the 24-pin (12x2) header. See Table 4 for connec-
tor pinout and pin descriptions. Use of this port
requires detailed knowledge of the AD9959 DDS
generator IC. You can use the ‘B’ command to test
your operation.

NOTE:

The table mode or table RAM is not accessible from 

the high speed port. The high speed port controls 

only the DDS ASIC.

NOTE:

For maximum interface speed, the high-speed inputs 

do not have additional protection against ESD 

damage beyond that provided by the CMOS inputs 

(+/-2kV, Human Body Model. +/-200 V, machine 

model) and 

47Ω 

series resistors.

3.12  All of the inputs are 3.3V VHCMOS compati-
ble and require:

V

il

 <= 0.4 volts

V

ih

 >= 2.7 volts

3.13  C

in

 on each pin is approximately 10pF (appli-

cation cable capacitance not included). The input

 

pins are series terminated with a 47

 resistor. It is

 

recommended that a series termination resistor of
50-100

 be used at each signal line source to pre-

vent reflections and ringing. The exact value will be

 

determined by your application circuitry and

 

cabling.

3.14  SER-, pin 4 of P1 must be held low to select

 

the high-speed interface. During initialization, EN-,

 

pin 11 of P1, is held high. When initialization is

 

complete it returns low.

3.15  Signal Outputs. There are eight signal outputs

 

on the DDS9m: four channels of Sine and the corre-
sponding LVCMOS/TTL. The Sine outputs are pro-
vided on MCX connectors (Johnson Components,

 

133-3701-133 or equivalent

)

 on the board edge.

 

Simply connect your 50

 application cable to

 

appropriate output. The LVCMOS outputs are on

 

wirepoints near the MCX outputs. The square pad is

 

the LVCMOS output and the round pad is ground. If

NOVATECH INSTRUMENTS

you are not using the LVCMOS/TTL output, it is
suggested that it be disabled by sending the 

“A D”

(default is disabled) command for best system noise
performance.

3.16  Mounting. Five mounting holes are provided
on the board. These holes are electrically connected
to circuit common and may be used for shield con-
nections. Clearance is provided for up to 3mm diam-
eter screws. Please allow at least 3 mm clearance on
the bottom side when mounting to a conductive
chassis or case. Refer to Table 3 and Figure 1 for
locations.

NOTE:

The DDS9m is cooled by convection. Verify that 
there is adequate free air flow around the board 

when mounting in an enclosure. Approximately 2 

Watts are dissipated.

4.0

Operation

4.1  Power on reset. After power is applied, the
DDS9m takes approximately 500ms to initialize.
Commands sent during this time will be ignored or
may cause erroneous operation.

4.2  Specifications are met within 15 minutes of
power-up in stable environment.

4.3  After the DDS9m has been installed in the cus-
tomer application system, all that is required for
operation is to send the appropriate serial commands
per Table 2.

4.4  The user host computer software must properly
format the serial commands. Incorrect formatting
will result in an error code being returned. See Table
1 for a list of error codes.

4.5  For maximum interface speed, it is suggested
that Echoing be disabled by the 

“E d”

 command.

This will allow the host to send characters at a faster
rate. Note that no flow control is provided. Depend-
ing upon your host, the DDS9m may not be able to
keep up with serial characters. The DDS9m will
respond with an 

“OK”

 for a correctly received data

command. You will have to verify correct operation
at your host rate.

Содержание DDS9m

Страница 1: ...m 170MHz 4 Channel Signal Generator Module DDS9m Table of Contents Section Page Contents 1 0 2 Description 2 0 2 Specifications 3 0 2 Hardware Installation 4 0 7 Operation 5 0 10 Theory of Operation 6...

Страница 2: ...o 40oC Stable to an addi tional 1ppm per year 18 to 28oC Internal Clock 2 5 EXTERNAL CLOCK IN LEVEL 0 2 to 0 5Vrms Sine or Square Wave 50 FREQUENCY 10MHz to 125MHz with multiplier of 4 to NOVATECH INS...

Страница 3: ...knowledge of the operation of the Analog Devices AD9959 DDS generator is required Since all registers are accessible it is possible to set the board into a non functional mode requiring a reset Appli...

Страница 4: ...the phase is not cleared default See Section 4 for details Vn N Set voltage level of output n In default the amplitude is set to the maximum approximately 1Vpp 4dBm into 50 N can range from 0 off to 1...

Страница 5: ...10 0 15 3 78 7 85 1 3 10 3 35 4 22 9 85 1 0 90 3 35 5 5 08 85 1 0 20 3 35 3 3V DC RS232 EXT CLK BATT B U HIGH SPEED INTERFACE VTUNE SINE OUTs LVCMOS OUTs MCXs WIRE PTs 0 0 MCX 115 2kBaud Select 1 2 3...

Страница 6: ...V be placed between the DDS9m and your system You may use the 3 3 V on pin 2 of P4 for this power up to 50mA Pin Number Function Type Pin Number Function Type 1 Ground Power Supply Com mon PS 2 3 3 V...

Страница 7: ...the MCX outputs The square pad is the LVCMOS output and the round pad is ground If NOVATECH INSTRUMENTS you are not using the LVCMOS TTL output it is suggested that it be disabled by sending the A D...

Страница 8: ...ernal clock will be assuming Kp is unchanged NOVATECH INSTRUMENTS Fn 4 4209530 where n is your selected channel NOTE You must account for your clock frequency error and calculation roundoff when using...

Страница 9: ...0000 03FF 00000000 00000000 000301 80 BC0000 0000 6102 21 Description Line 1 05F5E100 frequency in 0 1Hz steps per LSB 0000 phase setting 03FF amplitude setting default is scaling off 0000 linear ram...

Страница 10: ...TER_RESET PWR_DWN_CTL CS are set by the on board microcomputer at power up and are not accessible on the high speed interface The table mode or table RAM is not accessible from the high speed interfac...

Страница 11: ...data sheet your value of Kp times your selected clock frequency must not be between 160MHz and 255MHz For the internal clock values of Kp from 5 to 9 should not be used You may also need to set the VC...

Страница 12: ...xternal clock source NOVATECH INSTRUMENTS 6 11 Return the DDS9m to normal operation and default values by sending the CLR command 6 12 This concludes the verification test of the DDS9m 7 0 CALIBRATION...

Страница 13: ...xecution of table 0000 two byte RAM address T0 and T1 must be paired with same address aabbccdd four bytes frequency hexadecimal MSB first 4 bytes 0 1Hz resolution on LSB eeff phase offset hexadecimal...

Страница 14: ...fitness for a particular purpose In no event shall seller be liable for collateral or consequential damages Some states do not allow limitations or exclusion of consequential damages so this limitatio...

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