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DDS9m Manual

1.0

DESCRIPTION

1.1  The Model DDS9m is a four-channel Direct
Digital Synthesizer (DDS) on a small printed wiring
module with RS232 serial control. The DDS9m pro-
vides four independent sine wave and LVCMOS
output signals, which can be set from 0.1Hz to
171MHz in 0.1Hz steps when using the internal
VCTCXO clock (LVCMOS is optimized for outputs
greater than 1MHz and less 125MHz).

1.2  The DDS9m can also be used with an External
Clock input. An on-board programmable frequency
multiplier generates the master clock allowing user
configured frequency ranges. The multiplier can be
disabled for direct inputs up to 500MHz for opti-
mum phase noise performance. When used with the
same external clock source, multiple DDS9m are
phase synchronous.

2.0

SPECIFICATIONS

2.1  OUTPUTS

TYPES: Four Sine and LVCMOS simultaneously (four 
frequencies.)
IMPEDANCE: Sine: 50

Ω; 

LVCMOS: 50

Ω.

RANGE: 0.1Hz to 171MHz in 0.1Hz steps (Sine out, int.

 

clock).
SINE AMPLITUDE: approximately 1V

pp

 (+4dBm @ 

35MHz) into 50

Ω.

 Programmable from 0/1024 to 1023/

 

1024 of Full Scale (10-bits).
PHASE: Each channel 14-bits programmable.

 

FLATNESS: ±3dB from 1kHz to 150MHz referenced to 
amplitude at 35MHz, full scale.

2.2  LVCMOS AMPLITUDE

V

oh

 >=2.4V and V

ol

 <=0.4V when series terminated. Rise

 

and fall times <1.5ns. (1MHz< F

out

<125MHz)

2.3  CONTROL

Output frequencies, amplitudes (10-bits) and phases (14-
bits) are controlled by an RS232 serial port at 19.2kbaud.

 

All settings (except table mode data) can be saved in

 

non-volatile (EEPROM) memory via the RS232 port.

2.4  ACCURACY AND STABILITY

Accuracy: <±1.5ppm at 10 to 40

o

C. Stable to an addi-

tional ±1ppm per year, 18 to 28

o

C. (Internal Clock)

2.5  EXTERNAL CLOCK IN

LEVEL: 0.2 to 0.5Vrms Sine or Square Wave. 50

Ω.

 

FREQUENCY: 10MHz to 125MHz with multiplier of 4 to

NOVATECH INSTRUMENTS

20 enabled. Direct input of 1MHz to 500MHz.

2.6  SPECTRAL PURITY

 

(Typ. 50

 load, internal

clock, full-scale output)
Phase Noise: <-120dBc, 10kHz offset, 5MHz out.
Spurious:

<-60dBc below 10MHz (typ. 300MHz span)
<-60dBc below 40MHz
<-55dBc below 80MHz
<-50dBc below 160MHz

Harmonic: <-65dBc below 1MHz

<-55dBc below 20MHz
<-45dBc below 80MHz
<-35dBc below 160MHz

(channel-channel isolation: <-60dBc)

2.7  TABLE MODE

On-board 4Mb static ram holds up to 32,768 profile

 

points in table mode allowing a different output in 100

µ

s

 

increments. Channels 0 and 1 only.

2.8  POWER REQUIREMENTS

+3.14V to +3.46VDC@<750mA. Battery back-up 3.0V

 

nominal at <400

µ

A (2-AA, LR6, typical).

2.9  SIZE

82.6mm by 88.9mm circuit board. Max. height 10mm. 

2.10  CONNECTORS

MCX for Sine Outputs and EXT CLK IN. 2-pin header for 

+3.3V power and external back-up battery. 24-pin header

 

for high speed control. DE9 for Serial Control. 2-pin wire-

points for LVCMOS outputs.

3.0

 

HARDWARE INSTALLATION

WARNING:

The DDS9m contains static sensitive components. 

Before opening the package, follow appropriate 

static precautions. Failure to follow static 

precautions may damage the DDS9m.

3.1  Power Connection. Figure 1, Connection

 

Placement Diagram, shows a top view of the

 

DDS9m module. The required power of +3.3Volts

 

DC is applied through a 2-pin connector (mates with

 

Amp 640621-2). If you are using a Novatech Instru-
ments  supplied  connector,  Red  is  +3.3VDC  and

 

Black is the common return.

3.2  The quality of your power supply may affect the

 

performance of the DDS9m. The supply should be

 

free of ripple and noise (<50mV). Even though

Содержание DDS9m

Страница 1: ...m 170MHz 4 Channel Signal Generator Module DDS9m Table of Contents Section Page Contents 1 0 2 Description 2 0 2 Specifications 3 0 2 Hardware Installation 4 0 7 Operation 5 0 10 Theory of Operation 6...

Страница 2: ...o 40oC Stable to an addi tional 1ppm per year 18 to 28oC Internal Clock 2 5 EXTERNAL CLOCK IN LEVEL 0 2 to 0 5Vrms Sine or Square Wave 50 FREQUENCY 10MHz to 125MHz with multiplier of 4 to NOVATECH INS...

Страница 3: ...knowledge of the operation of the Analog Devices AD9959 DDS generator is required Since all registers are accessible it is possible to set the board into a non functional mode requiring a reset Appli...

Страница 4: ...the phase is not cleared default See Section 4 for details Vn N Set voltage level of output n In default the amplitude is set to the maximum approximately 1Vpp 4dBm into 50 N can range from 0 off to 1...

Страница 5: ...10 0 15 3 78 7 85 1 3 10 3 35 4 22 9 85 1 0 90 3 35 5 5 08 85 1 0 20 3 35 3 3V DC RS232 EXT CLK BATT B U HIGH SPEED INTERFACE VTUNE SINE OUTs LVCMOS OUTs MCXs WIRE PTs 0 0 MCX 115 2kBaud Select 1 2 3...

Страница 6: ...V be placed between the DDS9m and your system You may use the 3 3 V on pin 2 of P4 for this power up to 50mA Pin Number Function Type Pin Number Function Type 1 Ground Power Supply Com mon PS 2 3 3 V...

Страница 7: ...the MCX outputs The square pad is the LVCMOS output and the round pad is ground If NOVATECH INSTRUMENTS you are not using the LVCMOS TTL output it is suggested that it be disabled by sending the A D...

Страница 8: ...ernal clock will be assuming Kp is unchanged NOVATECH INSTRUMENTS Fn 4 4209530 where n is your selected channel NOTE You must account for your clock frequency error and calculation roundoff when using...

Страница 9: ...0000 03FF 00000000 00000000 000301 80 BC0000 0000 6102 21 Description Line 1 05F5E100 frequency in 0 1Hz steps per LSB 0000 phase setting 03FF amplitude setting default is scaling off 0000 linear ram...

Страница 10: ...TER_RESET PWR_DWN_CTL CS are set by the on board microcomputer at power up and are not accessible on the high speed interface The table mode or table RAM is not accessible from the high speed interfac...

Страница 11: ...data sheet your value of Kp times your selected clock frequency must not be between 160MHz and 255MHz For the internal clock values of Kp from 5 to 9 should not be used You may also need to set the VC...

Страница 12: ...xternal clock source NOVATECH INSTRUMENTS 6 11 Return the DDS9m to normal operation and default values by sending the CLR command 6 12 This concludes the verification test of the DDS9m 7 0 CALIBRATION...

Страница 13: ...xecution of table 0000 two byte RAM address T0 and T1 must be paired with same address aabbccdd four bytes frequency hexadecimal MSB first 4 bytes 0 1Hz resolution on LSB eeff phase offset hexadecimal...

Страница 14: ...fitness for a particular purpose In no event shall seller be liable for collateral or consequential damages Some states do not allow limitations or exclusion of consequential damages so this limitatio...

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