Novatech DDS9m Скачать руководство пользователя

Страница: 11 / 14

DDS9m Manual

for the internal (default) clock and the default PLL

Multiplier (Kp=15) settings.

5.4 Since the DDS IC is a sampled data system, the

output frequency is limited to a maximum of 1/2 the

system clock frequency (F

setting

<=2

-1). While it is

possible to generate an output near 50% of the clock,

the distortion may be unacceptable. Therefore, the

output is limited to approximately 40% of the sys-
tem clock and steep output filters are provided on

board: in this case 7th-order elliptical low pass fil-
ters.

5.5 If you are using an external clock and a Kp

which give a clock substantially lower than the

429.497MHz default internal clock, you may need

to filter the Outputs to obtain acceptable distortion

for your application. For best performance, set the

corner frequency at 40% or less of your external

clock frequency times Kp. The lower your filter as a

percentage of your clock frequency, the lower the

distortion.

NOTE:

Since filtering occurs before the signal is level

shifted to LVCMOS, the LVCMOS outputs may be

erratic or distorted when using low clock

frequencies. If you require an LVCMOS level signal

when using low clock frequencies, it is

recommended that you use an external comparator

or level shifter connected to the output of your

external filter.

5.6 For example, if you are using a 10MHz external

clock, with the default reference multiplier (Kp) of

15, then the internal clock is 150MHz. An optimal

filter for this frequency would then be approxi-
mately 60MHz (40% of 150MHz).

NOTE:

Per the Analog Devices AD9959 data sheet, your

value of Kp times your selected clock frequency must

not be between 160MHz and 255MHz. For the

internal clock, values of Kp from 5 to 9 should not

be used. You may also need to set the “VCO gain

control” bit in register FR1 as indicated by the

AD9959 data sheet. See paragraph 4.12.

NOVATECH INSTRUMENTS

6.0

PERFORMANCE TEST

6.1 Install the DDS9m as directed in the Serial
Operation part of Section 3. Connect your host con-
troller and operate the DDS9m per Section 4. The

test limits assume a stable environment of 18-28

NOTE:

Allow the DDS9m to warm up for at least 15 minutes

before performing any measurements. For best

results, the DDS9m should be verified in its installed

environment.

6.2 See Table 3 for a list of recommended test
equipment to perform the following measurements.

6.3 Verify Frequency Accuracy. To verify the fre-
quency of the DDS9m, set the output sequentially to
each value in Table 4, with the clock source set to
internal. Connect the recommended frequency
counter set to 50

Ω

termination and 0.1Hz resolution.

Verify the limits show in Table 4. Test all channels
to verify functionality of all outputs. If you do not
use an external reference for the frequency counter,
be sure to add the error of your counter to the toler-
ance. (LSD = Least Significant Digit on counter).

Table 3: Recommended Test Equipment

Item

Minimum

Specification

Recommended

Oscilloscope

300MHz, 50

Ω

Tektronix

TDS3032B

Ω

Termination