NI DAQ 6052E, Руководство пользователя

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Chapter 4 Connecting the Signals
© National Instruments Corporation 4-43 NI 6052E User Manual
GPCTR1_UP_DOWN Signal
This signal can be externally input on the DIO7 pin and is not available as
an output on the I/O connector. General-purpose counter 1 counts down
when this pin is at a logic low and counts up at a logic high. You can disable
this input so that the application software controls the up-down
functionality and leave the DIO7 pin free for general use.
Figure 4-39 shows the timing requirements for the GATE and SOURCE
input signals and the timing specifications for the OUT output signals of
the device.
Figure 4-39. GPCTR Timing Summary
The GATE and OUT signal transitions shown in Figure 4-39 are referenced
to the rising edge of the SOURCE signal. This timing diagram assumes that
the counters are programmed to count rising edges. If you program the
counter to count falling edges, the source signal is inverted and referenced
to the falling edge of the source signal in Figure 4-39.
The GATE input timing parameters are referenced to the signal at the
SOURCE input or to one of the internally generated signals on the device.
Figure 4-39 shows the GATE signal referenced to the rising edge of a
source signal. The gate must be valid (either high or low) for at least 10 ns
before the rising or falling edge of a source signal for the gate to take effect
t
sc
t
sc
t
sp
t
sp
t
sp
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
t
gsu
t
gsu
t
gh
t
gh
t
gw
t
gw
t
out
t
out
Source Clock Period
Source Pulse Width
Gate Setup Time
Gate Hold Time
Gate Pulse Width
Output Delay Time
50 ns minimum
23 ns minimum
10 ns minimum
0 ns minimum
10 ns minimum
80 ns maximum
SOURCE
GATE
OUT