Peak 555A User’s Guide
BIOS Setup 4-
20
SDRAM (CAS Lat/RAS-to-CAS)
This item allows you to select the CAS# latency for all SDRAM cycles and
RAS# to CAS# delay.
2/2
The timing type.
3/3 (Default)
The timing type.
SDRAM Speculative Read
This item is capable of allowing a DRAM read request to be generated
slightly before the address has been fully decoded. This can reduce all
read latencies.
More simply, the CPU will issue a read request and included with this
request is the place (address) in memory where the desired data is to be
found. This request is received by the DRAM controller. When it is
enabled, the controller will issue the read command slightly before it has
finished determining the address.
The Choice: Enabled, Disabled
(Default)
.
System BIOS Cacheable
Select Enabled allows caching of the system BIOS ROM at
F000h-FFFFFh, resulting in better system performance. However, if any
program writes to this memory area, a system error may result.
Enabled
BIOS access cached
Disabled (Default)
BIOS access not cached
Video BIOS Cacheable
Select Enabled allows caching of the video BIOS ROM at
C0000h-F7FFFh, resulting in better video performance. However, if any
program writes to this memory area, a system error may result.
Enabled
Video BIOS access cached
Disabled (Default)
Video BIOS access not cached