Peak 555A User’s Guide
BIOS Setup 4-
18
Auto Configuration
Auto Configuration selects predetermined optimal values of chipset
parameters. When Disabled, chipset parameters revert to setup
information stored in CMOS. Many fields in this screen are not available
when Auto Configuration is Enabled.
The Choice: Enabled (Default), Disabled.
Note: When this item is enabled, the pre-defined items will become
SHOW-ONLY.
DRAM Timimg
The DRAM timing is controlled by the DRAM Timing Registers. The
timings programmed into this register are dependent on the system
design. Slower rates may be required in certain system designs to
support loose layouts or slower memory.
60ns
DRAM Timing Type.
70ns (Default)
DRAM Timing Type.
DRAM Read Burst (EDO/FP)
This sets the timing for burst mode reads from two different
DRAM(EDO/FPM). Burst read and write requests are generated by the
CPU in four separate parts. The first part provides the location within the
DRAM where the read or write is to take place while the remaining three
parts provide the actual data. The lower the timing numbers, the faster
the system will address memory.
x222/x333
Read DRAM (EDO/FPM) timings are 2-2-2/3-3-3
x333/x444 (Default) Read DRAM (EDO/FPM) timings are 3-3-3/4-4-4
x444/x444
Read DRAM (EDO/FPM) timings are 4-4-4/4-4-4
DRAM Write Burst Timing
This sets the timing for burst mode writes from DRAM. Burst read and
write requests are generated by the CPU in four separate parts. The first
part provides the location within the DRAM where the read or write is to
take place while the remaining three parts provide the actual data. The
lower the timing numbers, the faster the system will address memory.
x222
Write DRAM timings are 2-2-2-2
x333 (Default)
Write DRAM timings are 3-3-3-3
x444
Write DRAM timings are 4-4-4-4
