Newport New Focus 8703, Руководство пользователя

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Theory of Operation 15
concern for ground loops associated with the control wiring. +V IN and SYS
GROUND should be routed one on top of the other (and with at least 0.5"-
wide traces).
You can use ground/power planes to route +V IN and SYS GROUND. Use
ground/power planes with caution: continuous planes can allow coupling
between the 8712 power and neighboring circuits. Power planes with
strategically placed slits to control current flow work best. +VIN and SYS
GROUND must not cross any plane slits in their paths to the power source.
The 8712 frame is connected to the internal ground. This connection is made
to improve shielding and reduce leakage currents in the 8712 frame. The four
mounting screws which are connected to the 8712 case should not be
connected to anything on the customer’s printed circuit board.
No additional filter capacitors are needed bV IN and SYSTEM
GROUND. A common-mode inductor can be used to reduce the effect of
switching power-supply noise and dynamic current.
3.5 Control Interface
This section describes the hardware aspects of the control interface:
•
MODE1, MODE0. These inputs are not optically isolated and should be
connected to SYSTEM GROUND or +5V OUT at the 8712 connector.
MODE1,0 should be optically isolated if you want to control these inputs
from the host computer. Include the 1 k
Ω
resistor connected in series to
the +5V OUT pin in any opto-coupler design calculations.
•
LIDLE, PULSE+/B, DIR+/A. These inputs are optically coupled. They
can be directly driven by an HC-TTL buffer like the 74HC244. A 0.06
W 470
Ω
resistor is connected in series with the opto-coupler input
diode to limit current. With 5V input, this resistor only dissipates 0.03
W. Clearly a higher control voltage could be used to drive the optically
coupled inputs. Calculate the current limiting resistor power dissipation
and add an external resistor if higher drive voltage is used. 3Volt logic
levels are marginal and not recommended for driving the 8712 optically
coupled inputs. When using LIDLE as control signal to activate the
output pulses, depending on power supply inrush current limit, the
typical value of delay time will be typically 400 ms.
•
LFAULT is an optically isolated output. It presents an open transistor to
the outside world. When on, LFAULT will sink 2.5 mA with 0.2 V
collector-emitter voltage. A 10 k
Ω
pull-up resistor connected to a +5 V
logic power supply (not +5VOUT) at the termination of LFAULT will
preserve the isolation of this output.
•
DGROUND is the return signal for all the optically coupled signals
mentioned above. It must be tied to digital ground at the source of
LIDLE, PULSE+/B, DIR+/A and the termination of LFAULT. Do not