NED
UME-0069-03
NUCLi7370AT6
37
4.3 Internal Circuit Configuration Block
The Internal Circuit Configuration block is shown below.
After the output signal from the CCD image sensor is converted by the A/D converter,
digital data processing is done in the FPGA video is output in the Camera Link
Medium configuration(at 8-bit 6-tap or 10-bit 3-tap output) .
COLOR CCD SENSOR (7300 pixels)
1 2 3・・・・ 3650 3651・・・・7299 7300
+12~15V
FPGA
Channel
Link
ドライバ1
動作インディケータ
(LED緑)
CC1±
CC2±
CC3±
CC4±
SerTFG±
LVDS
レシーバ
LVDS
ドライバ・
レシーバ
SerTC±
4
LVAL,FVAL
DVAL,CK
SP
PortA~C
丸型
コネクタ
HR10G
A/D
0/E
0/E
0/E
X0±,X1±,
X2±,X3±,
XClk±
0/E
0/E
0/E
A/D
B
R
G
Figure 4-3-1 Internal Circuit Configuration Block
Digital Processing flow in FPGA
The figure below shows the
digital processing flow in the FPGA.
Digital Data Processing block diagram
Video
(10bit)
From A/D
White reference
multiple
Line Delay
8 or 10 bit select
Video(8 or 10bit)
To Channel Link Driver
Figure 4-3-2 Digital Processing Block Diagram
4.4 Startup
After turning on, the camera runs a startup procedure before it starts getting images
and outputting data. It takes about six seconds.
The startup procedure is as follows.
(1) The camera initializes the hardware.
(2) Reads out the latest camera settings from the flash memory. (User settings if
any or factory default settings)
Channel
Link
Driver 1
LVDS
Receiver
LVDS
Driver
・
Receiver
Indicator
(LED Green)
Connector
HR10
G