33 NED
XCM8040SAT4 UME-0038-02
4.2.16 Setting the Pixel Readout Direction
Sets the pixel readout direction.
Format 2
CMD
□
VAL1 CR
CMD
rev
VAL1
0,1 (0:Forward, 1:Reverse)
<Example>
rev
□
1 CR (Reverse)
>OK
>rev 1
4.3 Digital Processing flow in FPGA
The
digital processing flow in FPGA is shown below.
Video(10bit)
From Sensor
-
x
White reference
multipl
Test Pattern
select
Black reference
substract
FPGA Processing block diagram
x
Video(8 or 10bit)
To Channel Link
Driver
Digital Gain
-
Digital Offset
8 or 10bit
select
Output Block
select
In Test Pattern mode, Black / White reference and Digital Gain /Offset will be skipped.
Figure 4-3-1 FPGA Processing Block Diagram
4.4 Startup
After turning on, the camera run a startup procedure before it starts getting
images and outputting data.
It takes about four seconds.
The startup procedure is as follows.
(1) The camera hardware initializes.
(2) Reads out the latest camera settings from the flash memory. (User
settings if any or factory default settings)
(3) Set up the camera with the setting value from the flash memory.
After those sequences, the camera is ready to get images and output data.
