CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION
Application Note U17121EJ1V1AN
66
(2) CLK to signal valid delay signals
Pin MIN.
MAX.
All PCI pins
2 ns
11 ns
The following specification values apply to the PCI bus timing (PCI CLK = 33 MHz).
Figure 4-1. Output Timing
CLK
T
VAL
Output delay
Figure 4-2. Input Timing
CLK
T
H
T
SU
Input
Inputs
valid
Table 4-1. 33 MHz Timing Parameters
Symbol
Parameter
MIN. (ns)
MAX. (ns)
T
VAL
CLK to signal valid delay bused signals
2
11
T
VAL
(ptp)
CLK to signal valid delay point to point signals
2
12
T
SU
Input setup time to CLK bused signals
7
T
SU
(ptp)
Input setup time to CLK point to point signals
10
T
H
Input hold time from CLK
0
4.6.3 SDRAM interface timing
The timing for interfacing with SDRAM depends on the external bus interface and the SDRAM to be connected.
Adjust the timing to suit the system.
Содержание V850E/MA1
Страница 2: ...Application Note U17121EJ1V1AN 2 MEMO ...
