NEC mPD784225 Series, Руководство пользователя

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CHAPTER 24 STANDBY FUNCTION
User’s Manual U12697EJ3V0UM
(1) HALT mode
(a) Settings and operating states of HALT mode
When set in the HALT mode in the low power consumption mode, set 75H in STBC. Table 24-9 shows the
operating states in the HALT mode.
Table 24-9. Operating States in HALT Mode
Item Operating State
Clock generator The clock supplied to the CPU stops, and only the main system clock stops oscillating.
CPU Operation disabled
Port (output latch) Holds the state before the HALT mode was set.
16-bit timer/event counter Operational when the watch timer output is selected as the count clock
(Select f
XT
as the count clock of the watch timer)
8-bit timer/event counters 1, 2 Operational when TI1 and TI2 are selected as the count clocks
8-bit timers 5 and 6 Operational when TI5 and TI6 are selected as the count clocks
Watch timer Operational only when f
XT
is selected as the count clock
Watchdog timer Operation disabled (counter is initialized)
A/D converter Operation disabled
D/A converter Operation enabled
Real-time output port Operational when an external trigger is used or TI1 and TI2 are selected as the count
clocks of the 8-bit timer counters 1 and 2
Serial interface Except I
2
C bus Operational only when an external input clock is selected as the serial clock
mode
I
2
C bus mode Operation disabled
External interrupt INTP0 to INTP5 Operation enabled
Bus lines during AD0 to AD7 High impedance
external expansion A8 to A19 Holds the state before the HALT mode was set.
ASTM Low level
WR, RD High level
WAIT Input state is retained.