Page 6-14
Vector-LP Radio Beacon Transmitter Technical Instruction Manual
Issue 1.1
Section 6 Theory of Operation
6.4.3.6 PDM FAULT DETECTOR
The PDM fault detector circuit contains a
voltage controlled switch that controls the
'set/'reset' status of the shutback latch
circuit and, in turn, controls the on/off
status of relay K1.
The PDM1 fault detector circuit consists of
U12A and its associated components.
R67/C58 form an integrator with a long
time constant, relative to the PDM
frequency. C58's charge voltage is applied
to U12A's inverting input and compared to
the 5 V reference voltage applied to its
non-inverting input from voltage divider
R70/R71/R72. U12A's output is an open
collector and has no influence when C58's
charge voltage is less positive than the
reference voltage. U12A's output will
switch to a current-sink-to-ground when
C58's charge voltage goes more positive
than the reference voltage.
During normal operation, C58 will charge
through R67 towards 15 V when the
PDM1 output is 15 V ('on time') and CR3
is reversed biased. It will instantly
discharge to 0 V, through CR3, when the
PDM1 output switches to 0 V ('off time').
The repetition rate of the PDM1 on/off
periods ensures the charge on C58 will not
exceed 5 V, provided each PDM1 cycle
contains an 'off time'. If a PDM failure
occurs such that it produces a continuous
'on time', C58 will charge more positively
than 5 V. U12A's output will switch to a
current-sink-to-ground and toggle the
shutback latch circuit to its 'set' state.
6.4.3.7 SHUTBACK LATCH
The shutback latch circuit inhibits the 'on
time' of the PDM output and, in turn, the
RF output of the transmitter whenever a
transmitter originated
Inhibit PDM
(P1-16)
command is applied. This circuit provides
additional protection to the transmitter's
RF power stages when faults are detected
or actions are initiated that may cause RF
stress current thresholds to be exceeded.
Its function is to de-energize K1 and
disconnect the
PDM 1
output from the
transmitter circuits when the PDM fault
detector output is a current-sink-to-ground
(logic low). It also inhibits the PDM
generator when relay K1 is de-energized
or when a logic true
inhibit PDM
command
is applied to P1-16.
U9A/U9B form a bistable flip/flop. The flip-
flop's output (U9-3) will be 15 V (logic
high) in its 'reset' state, and a current-sink-
to-ground (logic low) in its 'set' state.
Normally the
inhibit PDM
input and the
output of the PDM fault detector circuit,
which are the flip-flop's controlling inputs,
are open collector. 5 V (logic high) is
applied to U9-1 and U9-5 through their
pull-up resistors and the flip-flop is latched
in its 'reset' state. Relay K1 is held
energized and the PDM output is applied
to the transmitter circuits.
If a PDM fault is sensed, the PDM fault
detector circuit applies a current-sink-to-
ground (logic low) to U9-5 and causes the
flip-flop to switch to and latch in its 'set'
state. Relay K1 de-energizes and
disconnects the PDM output from the
transmitter circuits. The
PDM latch
output
(J1-11) is activated (5 V). This condition is
maintained until the flip-flop is reset by the
removal of the logic low from U9-5 (no
PDM fault) and the application of logic low
to U9-1 (a logic true current-sink-to-ground
reset PDM
command is applied to J1-1).
6.4.3.8 PDM INHIBIT
The PDM inhibit circuit consists of U9D,
transistor Q2, and their associated circuits.
Its function is to instantly clamp the output
of the PDM generator to ground (zero
carrier level) when a logic true (current-
sink-to-ground)
inhibit PDM
input is
applied to P1-16, or when the PDM fault
detector circuit senses a PDM fault and
the shutback latch circuit’s flip-flop is
latched in its ‘set’ state. When neither of
these conditions are true, the PDM inhibit
circuit has no influence.
