National ADC16DV160, Руководство пользователя

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SP16160CH1RB Reference Design Board User’s Guide
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7.0 System Performance
Figure 10 and Figure 11 show the typical SFDR and
SNR performance respectively over frequency. The
input signal is measured at -1, -3, and -6 dBFS and the
sample rate is 153.6 MSPS. Figure 12 (a) and (b) show
typical spectra for single and two-tone signals near 192
MHz.
7.1 Sources of Distortion
Harmonic distortion is introduced by the DVGA but
does not appear at the ADC input due to the high
attenuation of the anti-aliasing filter. Third-order
intermodulation distortion falls into the filter bandpass
and cannot be filtered out due to its proximity to the
bandwidth of interest. Two-tone test measurements
show that the third order products remain below 84
dBFS for a two-tone composite signal that has a 1 MHz
tone separation and swings 90% of full scale (-1 dBFS,
peak-to-peak).
The second- and third-order harmonic distortion (H2
and H3) that limits the SFDR of the system dominantly
occurs at the interface to the ADC. Charge kickback
from CMOS switches in the input stage of the ADC is a
significant cause of the harmonic distortion and can be
kept low with an empirical choice of capacitance in the
filter’s LC tank. Input signals near -1 dBFS amplitude
result in an SFDR typically greater than 82 dBFS
across the passband while -6 dBFS inputs typically
have an SFDR of greater than 92 as shown in Figure
10.
7.2 Sources of Noise
The SNR of the SP16160CH1RB is limited by the
thermal noise in the DVGA, thermal noise in the ADC,
and the jitter on the sampling clock.
Thermal noise in the ADC sets the hard SNR limit in
the system. An ideal 16-bit ADC is capable of a 98
dBFS SNR if quantization noise is the only contributor.
Additional noise in the ADC16DV160 limits the small
signal SNR to 78 dBFS and large signal SNR to 76.5
for a 192 MHz signal.
The signal bandwidth of the anti-aliasing filter is 20
MHz, considered here as the bandwidth with 0.5 dB
ripple, but the effective noise bandwidth is 44 MHz due
to the gradual roll-off of the filter profile. Noise from the
DVGA passes through the filter bandpass to contribute
to the total noise of the system. With the LMH6517
output noise density of 22 nV/sqrt(Hz) at 192 MHz and
a 1 dB insertion loss through a filter with a 44 MHz
ENBW, the small signal SNR due to the DVGA noise
(SNR
DVGA
) is 76.3 dBFS. The SNR
DVGA
can be
improved using a filter with a narrower effective noise
bandwidth. It can also be improved by increasing the
insertion loss of the filter but will result in worse
intermodulation distortion.
Jitter plays a role in limiting the SNR for large signal
inputs. A 192 MHz, -1 dBFS input signal yields phase
noise that results in an SNR, due to jitter (SNR
Jitter
), of
~75 dBFS. This SNR
Jitter
performance suggests a total
clock jitter of less than 200 fs.
Combining the noise sources from the ADC, DVGA,
and clock results in the total SNR (SNR
T
) of 71 dBFS
for a -1 dBFS input signal as shown in Figure 11. SNR
T
also improves for lower DVGA gain settings due to a
reduction in DVGA noise.
7.3 Wireless Base-Station Specific Performance
Base-station applications are concerned with
maximizing the sensitivity in a certain channel
bandwidth which can be limited by noise and spurs that
appear in the channel.
Blocking signals that appear close in frequency to the
channel not only limit the ability of the DVGA to apply
gain to the signal, but also contribute more noise to the
channel due to the phase noise skirt and the higher
broadband phase noise level that accompanies large
signals. To prevent overloading the ADC, a receiver’s
automation gain control (AGC) loop will keep the
blocking signal at a reasonable level such as -4 dBFS.
Assuming a GSM-type channel bandwidth of 200 kHz
and a -4 dBFS blocking signal that is 800 kHz from the
channel center, the SP16160CH1RB achieves a SNR
of 94 dBFS in the channel. In the absence of a blocking
signal, the system achieves a channel SNR of greater
than 99 dBFS.