National ADC16DV160, Руководство пользователя

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SP16160CH1RB Reference Design Board User’s Guide
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and buffering the clock reduces broadband white noise
present on the clock output from the LMK04031B.
Reducing the broadband noise is important because
the noise present at the wideband clock input of the
ADC convolves with the input signal during the
sampling process and aliases back into the first Nyquist
zone to degrade the SNR. A capacitive divider is then
used to reduce the clock amplitude to within tolerable
levels for the ADC.
6.5 Output Data
The dual channel, 16-bit digitized outputs from the
SP16160CH1RB reference board consist of 38 lines
that are arranged into 17 LVDS pairs. These 17 pairs
of lines carry the 16-bit output data (16 pairs) and the
DRDY output clock signal (1 pair) across the FutureBus
connector on the edge of the reference board to the
data capture hardware.
The data is clocked out of the ADC using the DRDY
signal with a dual date rate (DDR) such that the even
bits of both channels are available on the rising edge of
DRDY while the odd bits are available on the falling
edge.
Channel I data is available on the reference board at
pins A5/B5 (MSB +/-) through A12/B12 (LSB +/-) of the
FutureBus connector and Channel Q data is available
at pins A14/B14 through A21/B21. The DRDY signal is
at pins A13/B13.
Please see the SP16160CH1RB reference board
schematic in Section 10.0 of this guide and the
ADC16DV160 datasheet for further details.
6.6 Power requirements.
Power to the SP16160CH1RB evaluation board is
supplied through the green power connector labeled
“POWER” located along the side edge of the board.
The power supply must be capable of so5V up
to 1A. The SP16160CH1RB reference board draws
approximately 800 mA when digitizing a full scale input.